RV_TIMER Simulation Results

Thursday October 16 2025 16:09:11 UTC

GitHub Revision: b479ed8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	0.710s	78.519us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.820s	53.174us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.800s	51.660us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	2.090s	600.781us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.590s	46.714us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.300s	156.688us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.800s	51.660us	1	1	100.00
		rv_timer_csr_aliasing	0.590s	46.714us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.000s	578.230us	0	1	0.00
V2	disabled	rv_timer_disabled	2.120s	2.207ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	9.550s	8.297ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	9.550s	8.297ms	1	1	100.00
V2	stress	rv_timer_stress_all	2.180s	3.923ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.640s	14.251us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.670s	14.937us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.390s	168.849us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.390s	168.849us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.820s	53.174us	1	1	100.00
		rv_timer_csr_rw	0.800s	51.660us	1	1	100.00
		rv_timer_csr_aliasing	0.590s	46.714us	1	1	100.00
		rv_timer_same_csr_outstanding	0.770s	55.206us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.820s	53.174us	1	1	100.00
		rv_timer_csr_rw	0.800s	51.660us	1	1	100.00
		rv_timer_csr_aliasing	0.590s	46.714us	1	1	100.00
		rv_timer_same_csr_outstanding	0.770s	55.206us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	rv_timer_sec_cm	1.170s	176.241us	1	1	100.00
		rv_timer_tl_intg_err	1.320s	426.612us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.320s	426.612us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	0.640s	13.158us	1	1	100.00
V3	max_value	rv_timer_max	0.650s	101.205us	0	1	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	0.720s	23.842us	0	1	0.00
V3		TOTAL			1	3	33.33
		TOTAL			16	19	84.21

Failure Buckets

• UVM_ERROR (rv_timer_scoreboard.sv:365) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) has 1 failures:

  • Test rv_timer_max has 1 failures.

    • 0.rv_timer_max.26544811413929580353415883394413201402820529437526857429677631531526619088690
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log

        UVM_ERROR @ 101204562 ps: (rv_timer_scoreboard.sv:365) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (0x0 [0] vs 0x1 [1])
        UVM_INFO @ 101204562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 1 failures:

  • Test rv_timer_random_reset has 1 failures.

    • 0.rv_timer_random_reset.2258913580783934680593764006625367662251492547418030828556113167584210074746
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log

        UVM_FATAL @ 578230181 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xe3723304) == 0x1
        UVM_INFO @ 578230181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:

  • Test rv_timer_stress_all_with_rand_reset has 1 failures.

    • 0.rv_timer_stress_all_with_rand_reset.49248429171475639908727122248552635759865414896226229495245524807128096077253
      Line 101, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  23841912 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_rv_timer_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
        UVM_INFO @  23841912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---