SPI_DEVICE/1R1W Simulation Results

Thursday October 16 2025 16:09:11 UTC

GitHub Revision: b479ed8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	2.884m	105.446ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.260s	72.255us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.730s	51.696us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	10.420s	1.566ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	10.210s	934.304us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.300s	202.650us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.730s	51.696us	1	1	100.00
		spi_device_csr_aliasing	10.210s	934.304us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.990s	10.645us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.370s	259.434us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.030s	39.861us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.950s	15.354us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.010s	5.146us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.270s	185.039us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.270s	185.039us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	9.680s	6.486ms	1	1	100.00
		spi_device_tpm_sts_read	1.150s	129.260us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	21.850s	11.173ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	8.780s	7.087ms	1	1	100.00
		spi_device_flash_all	1.721m	99.905ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	3.520s	1.150ms	1	1	100.00
		spi_device_flash_all	1.721m	99.905ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	3.520s	1.150ms	1	1	100.00
		spi_device_flash_all	1.721m	99.905ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.721m	99.905ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.520s	605.520us	1	1	100.00
		spi_device_flash_all	1.721m	99.905ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.520s	605.520us	1	1	100.00
		spi_device_flash_all	1.721m	99.905ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.520s	605.520us	1	1	100.00
		spi_device_flash_all	1.721m	99.905ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.520s	605.520us	1	1	100.00
		spi_device_flash_all	1.721m	99.905ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.520s	605.520us	1	1	100.00
		spi_device_flash_all	1.721m	99.905ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	5.490s	274.362us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	11.100s	2.035ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	11.100s	2.035ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	11.100s	2.035ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	10.210s	5.364ms	1	1	100.00
		spi_device_read_buffer_direct	2.810s	230.094us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	11.100s	2.035ms	1	1	100.00
		spi_device_flash_all	1.721m	99.905ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.721m	99.905ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.721m	99.905ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.580s	979.192us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.580s	979.192us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	2.884m	105.446ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	7.354m	71.454ms	1	1	100.00
V2	stress_all	spi_device_stress_all	9.930s	3.654ms	1	1	100.00
V2	alert_test	spi_device_alert_test	0.920s	62.016us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.900s	19.098us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.370s	299.447us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.370s	299.447us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.260s	72.255us	1	1	100.00
		spi_device_csr_rw	1.730s	51.696us	1	1	100.00
		spi_device_csr_aliasing	10.210s	934.304us	1	1	100.00
		spi_device_same_csr_outstanding	2.460s	275.146us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.260s	72.255us	1	1	100.00
		spi_device_csr_rw	1.730s	51.696us	1	1	100.00
		spi_device_csr_aliasing	10.210s	934.304us	1	1	100.00
		spi_device_same_csr_outstanding	2.460s	275.146us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.630s	179.583us	1	1	100.00
		spi_device_tl_intg_err	7.230s	634.726us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	7.230s	634.726us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	2.427m	30.411ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.61959225413389554352607306976614798537153551231548671670671733909147725474162
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @  11242564 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[109])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @  11242564 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @  11242564 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[1005])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.114849323047662732979743643105245183219696706087725733260955678991383476366799
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   2432225 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xce11dd [110011100001000111011101] vs 0x0 [0])
        UVM_ERROR @   2469225 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa8f1c4 [101010001111000111000100] vs 0x0 [0])
        UVM_ERROR @   2529225 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2c483a [1011000100100000111010] vs 0x0 [0])
        UVM_ERROR @   2568225 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x948569 [100101001000010101101001] vs 0x0 [0])
        UVM_ERROR @   2587225 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf26a95 [111100100110101010010101] vs 0x0 [0])