SRAM_CTRL/MAIN Simulation Results

Thursday October 16 2025 16:09:11 UTC

GitHub Revision: b479ed8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	20.750s	1.520ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.770s	70.704us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.650s	35.806us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.140s	64.081us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.780s	43.003us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.420s	1.478ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.650s	35.806us	1	1	100.00
		sram_ctrl_csr_aliasing	0.780s	43.003us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.943m	31.420ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.604m	11.356ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	9.687m	32.237ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	1.335m	3.985ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	21.397m	107.887ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	2.307m	16.270ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	34.790s	8.931ms	1	1	100.00
V2	executable	sram_ctrl_executable	13.300m	50.057ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	11.290s	1.084ms	1	1	100.00
		sram_ctrl_partial_access_b2b	5.717m	82.742ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	57.640s	3.156ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	45.960s	806.990us	1	1	100.00
		sram_ctrl_throughput_w_readback	1.005m	919.293us	1	1	100.00
V2	regwen	sram_ctrl_regwen	9.381m	15.399ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.170s	413.716us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	38.912m	513.509ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.770s	52.325us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	1.380s	169.992us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	1.380s	169.992us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.770s	70.704us	1	1	100.00
		sram_ctrl_csr_rw	0.650s	35.806us	1	1	100.00
		sram_ctrl_csr_aliasing	0.780s	43.003us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.830s	19.495us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.770s	70.704us	1	1	100.00
		sram_ctrl_csr_rw	0.650s	35.806us	1	1	100.00
		sram_ctrl_csr_aliasing	0.780s	43.003us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.830s	19.495us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	34.980s	30.761ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.870s	834.720ns	0	1	0.00
		sram_ctrl_tl_intg_err	2.310s	381.266us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.870s	834.720ns	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.310s	381.266us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	9.381m	15.399ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	9.381m	15.399ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.650s	35.806us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	13.300m	50.057ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	13.300m	50.057ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	13.300m	50.057ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	34.790s	8.931ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	6.340s	1.365ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	34.980s	30.761ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	5.710s	5.484ms	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	20.750s	1.520ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	20.750s	1.520ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	13.300m	50.057ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.870s	834.720ns	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	34.790s	8.931ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.870s	834.720ns	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.870s	834.720ns	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	20.750s	1.520ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.870s	834.720ns	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	24.290s	854.203us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• Offending '(depth_o <= *'(Depth))' has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.8342146356423212158593131836331505750340263025633261949982117230522571726470
      Line 96, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @    834720 ps: (prim_fifo_sync.sv:211) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @    834720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---