SRAM_CTRL/RET Simulation Results

Thursday October 16 2025 16:09:11 UTC

GitHub Revision: `b479ed8`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	9.950s	644.881us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.690s	13.438us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.800s	21.878us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.100s	51.346us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.970s	89.538us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	0.790s	101.828us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.800s	21.878us	1	1	100.00
		sram_ctrl_csr_aliasing	0.970s	89.538us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.400s	78.146us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.330s	374.352us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	29.460s	4.964ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.510m	2.882ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	14.990s	1.617ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	5.396m	10.922ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	8.810s	4.432ms	1	1	100.00
V2	executable	sram_ctrl_executable	2.816m	1.057ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	38.150s	199.312us	1	1	100.00
		sram_ctrl_partial_access_b2b	3.656m	85.248ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	30.050s	118.681us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	1.190s	37.073us	1	1	100.00
		sram_ctrl_throughput_w_readback	25.640s	219.969us	1	1	100.00
V2	regwen	sram_ctrl_regwen	13.088m	71.354ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	0.700s	50.781us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	37.488m	207.494ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.750s	60.444us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.710s	1.317ms	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.710s	1.317ms	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.690s	13.438us	1	1	100.00
		sram_ctrl_csr_rw	0.800s	21.878us	1	1	100.00
		sram_ctrl_csr_aliasing	0.970s	89.538us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.760s	13.206us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.690s	13.438us	1	1	100.00
		sram_ctrl_csr_rw	0.800s	21.878us	1	1	100.00
		sram_ctrl_csr_aliasing	0.970s	89.538us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.760s	13.206us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.620s	1.501ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.590s	3.003us	0	1	0.00
		sram_ctrl_tl_intg_err	1.380s	156.703us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.590s	3.003us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.380s	156.703us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	13.088m	71.354ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	13.088m	71.354ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.800s	21.878us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	2.816m	1.057ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	2.816m	1.057ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	2.816m	1.057ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	8.810s	4.432ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	0.880s	202.163us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.620s	1.501ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	0.910s	30.022us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	9.950s	644.881us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	9.950s	644.881us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	2.816m	1.057ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.590s	3.003us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	8.810s	4.432ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.590s	3.003us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.590s	3.003us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	9.950s	644.881us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.590s	3.003us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	25.310s	3.525ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			29	31	93.55

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:1142) [sram_ctrl_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test sram_ctrl_stress_all_with_rand_reset has 1 failures.
  - 0.sram_ctrl_stress_all_with_rand_reset.82646600630605774857197616491460001730893045672611897987824775472908932565613
    Line 194, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3524552874 ps: (cip_base_vseq.sv:1142) [uvm_test_top.env.virtual_sequencer.sram_ctrl_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 3524552874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 1 failures:

Test sram_ctrl_sec_cm has 1 failures.

0.sram_ctrl_sec_cm.77102542874026119372915154473241632782843834894260522244821086754931708202381
Line 98, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

      Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.tlul_assert_device_ram.gen_device.gen_d2h.respMustHaveReq_A: started at 2997667ps failed at 2997667ps
      Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
  "src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv", 211: tb.dut.u_tlul_adapter_sram_racl.tlul_adapter_sram.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth: started at 3002769ps failed at 3002769ps
      Offending '(depth_o <= 2'(Depth))'