UART Simulation Results

Thursday October 16 2025 16:09:11 UTC

GitHub Revision: b479ed8

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	3.330s	881.374us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.690s	24.558us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.610s	14.249us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.390s	721.780us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.830s	101.143us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.050s	43.517us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.610s	14.249us	1	1	100.00
		uart_csr_aliasing	0.830s	101.143us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	31.800s	44.212ms	1	1	100.00
V2	parity	uart_smoke	3.330s	881.374us	1	1	100.00
		uart_tx_rx	31.800s	44.212ms	1	1	100.00
V2	parity_error	uart_intr	12.820s	31.668ms	1	1	100.00
		uart_rx_parity_err	53.680s	84.885ms	1	1	100.00
V2	watermark	uart_tx_rx	31.800s	44.212ms	1	1	100.00
		uart_intr	12.820s	31.668ms	1	1	100.00
V2	fifo_full	uart_fifo_full	1.945m	191.090ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	25.890s	20.748ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	10.260s	8.446ms	1	1	100.00
V2	rx_frame_err	uart_intr	12.820s	31.668ms	1	1	100.00
V2	rx_break_err	uart_intr	12.820s	31.668ms	1	1	100.00
V2	rx_timeout	uart_intr	12.820s	31.668ms	1	1	100.00
V2	perf	uart_perf	51.130s	11.834ms	1	1	100.00
V2	sys_loopback	uart_loopback	1.610s	1.833ms	1	1	100.00
V2	line_loopback	uart_loopback	1.610s	1.833ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	25.000s	205.139ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.600s	2.814ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.400s	773.995us	1	1	100.00
V2	rx_oversample	uart_rx_oversample	14.420s	3.566ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	4.454m	130.548ms	1	1	100.00
V2	stress_all	uart_stress_all	2.138m	166.411ms	0	1	0.00
V2	alert_test	uart_alert_test	0.820s	31.190us	1	1	100.00
V2	intr_test	uart_intr_test	0.700s	26.024us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.470s	50.209us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.470s	50.209us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.690s	24.558us	1	1	100.00
		uart_csr_rw	0.610s	14.249us	1	1	100.00
		uart_csr_aliasing	0.830s	101.143us	1	1	100.00
		uart_same_csr_outstanding	0.800s	37.137us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.690s	24.558us	1	1	100.00
		uart_csr_rw	0.610s	14.249us	1	1	100.00
		uart_csr_aliasing	0.830s	101.143us	1	1	100.00
		uart_same_csr_outstanding	0.800s	37.137us	1	1	100.00
V2		TOTAL			16	18	88.89
V2S	tl_intg_err	uart_sec_cm	1.020s	38.153us	1	1	100.00
		uart_tl_intg_err	1.010s	93.114us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.010s	93.114us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	21.530s	2.261ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			25	27	92.59

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 2 failures:

  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.97532684400086701875100215871916751917337543510570140933425699230883101722008
      Line 80, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 203578236124 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 203586611124 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 204248361124 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 6,                                 clk_pulses: 0
        UVM_ERROR @ 204248486124 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 204249361124 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (46 [0x2e] vs 255 [0xff]) reg name: uart_reg_block.rdata
      

  • Test uart_stress_all has 1 failures.

    • 0.uart_stress_all.2320759316992399150388614984607692090360030015762464582369856580335615744520
      Line 90, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_stress_all/latest/run.log

        UVM_ERROR @ 165774899277 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 165779160121 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 166376634797 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 166391765141 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 166391765141 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0