AES/UNMASKED Simulation Results

Monday October 20 2025 16:04:01 UTC

GitHub Revision: cf33148

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	1.000s	57.518us	1	1	100.00
V1	smoke	aes_smoke	2.000s	60.298us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	2.000s	118.505us	1	1	100.00
V1	csr_rw	aes_csr_rw	2.000s	69.601us	1	1	100.00
V1	csr_bit_bash	aes_csr_bit_bash	4.000s	295.583us	1	1	100.00
V1	csr_aliasing	aes_csr_aliasing	2.000s	294.320us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	2.000s	86.863us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	2.000s	69.601us	1	1	100.00
		aes_csr_aliasing	2.000s	294.320us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	algorithm	aes_smoke	2.000s	60.298us	1	1	100.00
		aes_config_error	3.000s	104.601us	1	1	100.00
		aes_stress	2.000s	82.617us	1	1	100.00
V2	key_length	aes_smoke	2.000s	60.298us	1	1	100.00
		aes_config_error	3.000s	104.601us	1	1	100.00
		aes_stress	2.000s	82.617us	1	1	100.00
V2	back2back	aes_stress	2.000s	82.617us	1	1	100.00
		aes_b2b	6.000s	158.274us	1	1	100.00
V2	backpressure	aes_stress	2.000s	82.617us	1	1	100.00
V2	multi_message	aes_smoke	2.000s	60.298us	1	1	100.00
		aes_config_error	3.000s	104.601us	1	1	100.00
		aes_stress	2.000s	82.617us	1	1	100.00
		aes_alert_reset	2.000s	140.166us	1	1	100.00
V2	failure_test	aes_man_cfg_err	2.000s	58.436us	1	1	100.00
		aes_config_error	3.000s	104.601us	1	1	100.00
		aes_alert_reset	2.000s	140.166us	1	1	100.00
V2	trigger_clear_test	aes_clear	3.000s	399.866us	1	1	100.00
V2	nist_test_vectors	aes_nist_vectors	4.000s	154.906us	1	1	100.00
V2	reset_recovery	aes_alert_reset	2.000s	140.166us	1	1	100.00
V2	stress	aes_stress	2.000s	82.617us	1	1	100.00
V2	sideload	aes_stress	2.000s	82.617us	1	1	100.00
		aes_sideload	2.000s	66.468us	1	1	100.00
V2	deinitialization	aes_deinit	2.000s	70.388us	1	1	100.00
V2	stress_all	aes_stress_all	8.000s	490.158us	1	1	100.00
V2	alert_test	aes_alert_test	1.000s	85.418us	1	1	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	3.000s	74.634us	1	1	100.00
V2	tl_d_illegal_access	aes_tl_errors	3.000s	74.634us	1	1	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	2.000s	118.505us	1	1	100.00
		aes_csr_rw	2.000s	69.601us	1	1	100.00
		aes_csr_aliasing	2.000s	294.320us	1	1	100.00
		aes_same_csr_outstanding	3.000s	248.055us	1	1	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	2.000s	118.505us	1	1	100.00
		aes_csr_rw	2.000s	69.601us	1	1	100.00
		aes_csr_aliasing	2.000s	294.320us	1	1	100.00
		aes_same_csr_outstanding	3.000s	248.055us	1	1	100.00
V2		TOTAL			13	13	100.00
V2S	reseeding	aes_reseed	3.000s	101.353us	1	1	100.00
V2S	fault_inject	aes_fi	2.000s	126.885us	1	1	100.00
		aes_control_fi	2.000s	50.392us	1	1	100.00
		aes_cipher_fi	3.000s	61.479us	1	1	100.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	1.000s	115.732us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	1.000s	115.732us	1	1	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	1.000s	115.732us	1	1	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	1.000s	115.732us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	3.000s	449.436us	1	1	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	877.976us	1	1	100.00
		aes_tl_intg_err	2.000s	223.683us	1	1	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	2.000s	223.683us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	2.000s	140.166us	1	1	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	1.000s	115.732us	1	1	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	2.000s	60.298us	1	1	100.00
		aes_stress	2.000s	82.617us	1	1	100.00
		aes_alert_reset	2.000s	140.166us	1	1	100.00
		aes_core_fi	2.000s	64.587us	1	1	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	1.000s	115.732us	1	1	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	2.000s	69.994us	1	1	100.00
		aes_stress	2.000s	82.617us	1	1	100.00
V2S	sec_cm_key_sideload	aes_stress	2.000s	82.617us	1	1	100.00
		aes_sideload	2.000s	66.468us	1	1	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	2.000s	69.994us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	2.000s	69.994us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	2.000s	69.994us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	2.000s	69.994us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	2.000s	69.994us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	2.000s	82.617us	1	1	100.00
V2S	sec_cm_key_masking	aes_stress	2.000s	82.617us	1	1	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	2.000s	126.885us	1	1	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	2.000s	126.885us	1	1	100.00
		aes_control_fi	2.000s	50.392us	1	1	100.00
		aes_cipher_fi	3.000s	61.479us	1	1	100.00
		aes_ctr_fi	2.000s	58.052us	1	1	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	2.000s	126.885us	1	1	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	2.000s	126.885us	1	1	100.00
		aes_control_fi	2.000s	50.392us	1	1	100.00
		aes_cipher_fi	3.000s	61.479us	1	1	100.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	3.000s	61.479us	1	1	100.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	2.000s	126.885us	1	1	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	2.000s	126.885us	1	1	100.00
		aes_control_fi	2.000s	50.392us	1	1	100.00
		aes_ctr_fi	2.000s	58.052us	1	1	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	2.000s	126.885us	1	1	100.00
		aes_control_fi	2.000s	50.392us	1	1	100.00
		aes_cipher_fi	3.000s	61.479us	1	1	100.00
		aes_ctr_fi	2.000s	58.052us	1	1	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	2.000s	140.166us	1	1	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	2.000s	126.885us	1	1	100.00
		aes_control_fi	2.000s	50.392us	1	1	100.00
		aes_cipher_fi	3.000s	61.479us	1	1	100.00
		aes_ctr_fi	2.000s	58.052us	1	1	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	2.000s	126.885us	1	1	100.00
		aes_control_fi	2.000s	50.392us	1	1	100.00
		aes_cipher_fi	3.000s	61.479us	1	1	100.00
		aes_ctr_fi	2.000s	58.052us	1	1	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	2.000s	126.885us	1	1	100.00
		aes_control_fi	2.000s	50.392us	1	1	100.00
		aes_ctr_fi	2.000s	58.052us	1	1	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	2.000s	126.885us	1	1	100.00
		aes_control_fi	2.000s	50.392us	1	1	100.00
		aes_cipher_fi	3.000s	61.479us	1	1	100.00
V2S		TOTAL			11	11	100.00
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	9.000s	7.845ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			31	32	96.88

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (* [*] vs * [*]) Regname: aes_reg_block.ctrl_shadowed reset value: * has 1 failures:
  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.101429683847510914522438179168446614062735223779102399193386880826618439078723
      Line 167, in log /nightly/current_run/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7844615263 ps: (csr_utils_pkg.sv:458) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (4353 [0x1101] vs 4481 [0x1181]) Regname: aes_reg_block.ctrl_shadowed reset value: 0x1181
        UVM_INFO @ 7844615263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---