DMA Simulation Results

Monday October 20 2025 16:04:01 UTC

GitHub Revision: cf33148

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	5.000s	298.658us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	4.000s	258.514us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	6.000s	327.388us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	2.000s	32.236us	1	1	100.00
V1	csr_rw	dma_csr_rw	1.000s	18.238us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	14.000s	3.995ms	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	3.000s	963.592us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	1.000s	24.699us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	1.000s	18.238us	1	1	100.00
		dma_csr_aliasing	3.000s	963.592us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	41.000s	3.677ms	1	1	100.00
V2	dma_memory_tl_error	dma_memory_stress	10.833m	62.411ms	1	1	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	4.217m	91.892ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	4.217m	91.892ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	10.833m	62.411ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	14.733m	179.453ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	4.217m	91.892ms	1	1	100.00
V2	dma_abort	dma_abort	8.000s	2.130ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	1.950m	8.409ms	1	1	100.00
V2	alert_test	dma_alert_test	2.000s	32.497us	1	1	100.00
V2	intr_test	dma_intr_test	2.000s	43.425us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	3.000s	291.223us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	3.000s	291.223us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	2.000s	32.236us	1	1	100.00
		dma_csr_rw	1.000s	18.238us	1	1	100.00
		dma_csr_aliasing	3.000s	963.592us	1	1	100.00
		dma_same_csr_outstanding	2.000s	51.665us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	2.000s	32.236us	1	1	100.00
		dma_csr_rw	1.000s	18.238us	1	1	100.00
		dma_csr_aliasing	3.000s	963.592us	1	1	100.00
		dma_same_csr_outstanding	2.000s	51.665us	1	1	100.00
V2		TOTAL			10	10	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	9.000s	650.659us	1	1	100.00
		dma_generic_stress	14.733m	179.453ms	1	1	100.00
		dma_handshake_stress	4.217m	91.892ms	1	1	100.00
V2S	dma_config_lock	dma_config_lock	5.000s	1.303ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	3.000s	385.923us	1	1	100.00
		dma_sec_cm	2.000s	11.280us	1	1	100.00
V2S		TOTAL			4	4	100.00
	Unmapped tests	dma_short_transfer	1.383m	29.734ms	1	1	100.00
		dma_longer_transfer	3.000s	1.186ms	1	1	100.00
		dma_stress_all_with_rand_reset	31.000s	1.271ms	0	1	0.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.107684663236085005587253070014109570234355516410453844339987173671711595725516
      Line 141, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1270906524ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10004 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1270906524ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---