EDN Simulation Results

Monday October 20 2025 16:04:01 UTC

GitHub Revision: cf33148

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.940s	47.543us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.070s	20.236us	1	1	100.00
V1	csr_rw	edn_csr_rw	0.770s	23.095us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	2.380s	59.325us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	0.980s	61.538us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	0.970s	45.152us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.770s	23.095us	1	1	100.00
		edn_csr_aliasing	0.980s	61.538us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	0.900s	58.853us	1	1	100.00
V2	csrng_commands	edn_genbits	0.900s	58.853us	1	1	100.00
V2	genbits	edn_genbits	0.900s	58.853us	1	1	100.00
V2	interrupts	edn_intr	0.980s	25.478us	1	1	100.00
V2	alerts	edn_alert	1.070s	41.039us	1	1	100.00
V2	errs	edn_err	1.140s	31.203us	1	1	100.00
V2	disable	edn_disable	0.910s	12.096us	1	1	100.00
		edn_disable_auto_req_mode	1.080s	29.418us	1	1	100.00
V2	stress_all	edn_stress_all	2.420s	152.843us	1	1	100.00
V2	intr_test	edn_intr_test	0.870s	23.426us	1	1	100.00
V2	alert_test	edn_alert_test	0.990s	20.171us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	1.350s	134.653us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	1.350s	134.653us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.070s	20.236us	1	1	100.00
		edn_csr_rw	0.770s	23.095us	1	1	100.00
		edn_csr_aliasing	0.980s	61.538us	1	1	100.00
		edn_same_csr_outstanding	1.110s	59.087us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.070s	20.236us	1	1	100.00
		edn_csr_rw	0.770s	23.095us	1	1	100.00
		edn_csr_aliasing	0.980s	61.538us	1	1	100.00
		edn_same_csr_outstanding	1.110s	59.087us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	5.520s	5.510ms	1	1	100.00
		edn_tl_intg_err	2.300s	130.706us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.870s	19.342us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.070s	41.039us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	5.520s	5.510ms	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	5.520s	5.510ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	5.520s	5.510ms	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	5.520s	5.510ms	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.070s	41.039us	1	1	100.00
		edn_sec_cm	5.520s	5.510ms	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.070s	41.039us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.300s	130.706us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.452m	4.761ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00