HMAC Simulation Results

Monday October 20 2025 16:04:01 UTC

GitHub Revision: cf33148

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 7.840s 981.203us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.860s 190.095us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.670s 16.230us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 8.260s 9.573ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 5.860s 2.295ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.400s 133.863us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.670s 16.230us 1 1 100.00
hmac_csr_aliasing 5.860s 2.295ms 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 53.900s 8.602ms 1 1 100.00
V2 back_pressure hmac_back_pressure 50.590s 4.740ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 7.450s 178.254us 1 1 100.00
hmac_test_sha384_vectors 19.010s 478.412us 1 1 100.00
hmac_test_sha512_vectors 18.530s 480.102us 1 1 100.00
hmac_test_hmac256_vectors 7.850s 269.545us 1 1 100.00
hmac_test_hmac384_vectors 7.330s 1.058ms 1 1 100.00
hmac_test_hmac512_vectors 12.480s 424.802us 1 1 100.00
V2 burst_wr hmac_burst_wr 11.170s 1.246ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 2.499m 2.519ms 1 1 100.00
V2 error hmac_error 1.298m 8.194ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 58.700s 1.721ms 1 1 100.00
V2 save_and_restore hmac_smoke 7.840s 981.203us 1 1 100.00
hmac_long_msg 53.900s 8.602ms 1 1 100.00
hmac_back_pressure 50.590s 4.740ms 1 1 100.00
hmac_datapath_stress 2.499m 2.519ms 1 1 100.00
hmac_burst_wr 11.170s 1.246ms 1 1 100.00
hmac_stress_all 23.693m 204.147ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 7.840s 981.203us 1 1 100.00
hmac_long_msg 53.900s 8.602ms 1 1 100.00
hmac_back_pressure 50.590s 4.740ms 1 1 100.00
hmac_datapath_stress 2.499m 2.519ms 1 1 100.00
hmac_wipe_secret 58.700s 1.721ms 1 1 100.00
hmac_test_sha256_vectors 7.450s 178.254us 1 1 100.00
hmac_test_sha384_vectors 19.010s 478.412us 1 1 100.00
hmac_test_sha512_vectors 18.530s 480.102us 1 1 100.00
hmac_test_hmac256_vectors 7.850s 269.545us 1 1 100.00
hmac_test_hmac384_vectors 7.330s 1.058ms 1 1 100.00
hmac_test_hmac512_vectors 12.480s 424.802us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 7.840s 981.203us 1 1 100.00
hmac_long_msg 53.900s 8.602ms 1 1 100.00
hmac_back_pressure 50.590s 4.740ms 1 1 100.00
hmac_datapath_stress 2.499m 2.519ms 1 1 100.00
hmac_burst_wr 11.170s 1.246ms 1 1 100.00
hmac_error 1.298m 8.194ms 1 1 100.00
hmac_wipe_secret 58.700s 1.721ms 1 1 100.00
hmac_test_sha256_vectors 7.450s 178.254us 1 1 100.00
hmac_test_sha384_vectors 19.010s 478.412us 1 1 100.00
hmac_test_sha512_vectors 18.530s 480.102us 1 1 100.00
hmac_test_hmac256_vectors 7.850s 269.545us 1 1 100.00
hmac_test_hmac384_vectors 7.330s 1.058ms 1 1 100.00
hmac_test_hmac512_vectors 12.480s 424.802us 1 1 100.00
hmac_stress_all 23.693m 204.147ms 1 1 100.00
V2 stress_all hmac_stress_all 23.693m 204.147ms 1 1 100.00
V2 alert_test hmac_alert_test 0.570s 44.539us 1 1 100.00
V2 intr_test hmac_intr_test 0.620s 32.098us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.910s 179.180us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.910s 179.180us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.860s 190.095us 1 1 100.00
hmac_csr_rw 0.670s 16.230us 1 1 100.00
hmac_csr_aliasing 5.860s 2.295ms 1 1 100.00
hmac_same_csr_outstanding 0.940s 24.676us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.860s 190.095us 1 1 100.00
hmac_csr_rw 0.670s 16.230us 1 1 100.00
hmac_csr_aliasing 5.860s 2.295ms 1 1 100.00
hmac_same_csr_outstanding 0.940s 24.676us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 0.920s 347.568us 1 1 100.00
hmac_tl_intg_err 2.850s 1.902ms 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.850s 1.902ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 7.840s 981.203us 1 1 100.00
V3 stress_reset hmac_stress_reset 1.140s 23.213us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.062m 5.086ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 0.920s 78.501us 1 1 100.00
TOTAL 28 28 100.00