I2C Simulation Results

Monday October 20 2025 16:04:01 UTC

GitHub Revision: cf33148

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	16.670s	1.386ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	10.270s	1.774ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.690s	24.938us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.770s	21.269us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.890s	523.202us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	0.990s	54.796us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.150s	32.038us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.770s	21.269us	1	1	100.00
		i2c_csr_aliasing	0.990s	54.796us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	0.910s	30.244us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	0.990s	40.131us	0	1	0.00
V2	host_maxperf	i2c_host_perf	7.001m	26.259ms	1	1	100.00
V2	host_override	i2c_host_override	0.960s	90.932us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	2.285m	37.018ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	54.600s	1.265ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	0.950s	332.463us	1	1	100.00
		i2c_host_fifo_fmt_empty	5.470s	813.194us	1	1	100.00
		i2c_host_fifo_reset_rx	6.920s	171.746us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.237m	4.298ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	10.040s	829.891us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.260s	71.220us	0	1	0.00
V2	target_glitch	i2c_target_glitch	2.420s	519.824us	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	1.098m	50.576ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.630s	680.440us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	8.140s	569.031us	1	1	100.00
		i2c_target_intr_smoke	4.450s	2.526ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.620s	311.350us	1	1	100.00
		i2c_target_fifo_reset_tx	1.830s	821.925us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	7.194m	64.811ms	1	1	100.00
		i2c_target_stress_rd	8.140s	569.031us	1	1	100.00
		i2c_target_intr_stress_wr	13.350s	10.944ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	4.810s	2.212ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	5.230s	1.444ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	2.550s	1.259ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.210s	727.811us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	1.260s	180.669us	1	1	100.00
		i2c_target_fifo_watermarks_tx	0.680s	94.885us	0	1	0.00
V2	host_mode_config_perf	i2c_host_perf	7.001m	26.259ms	1	1	100.00
		i2c_host_perf_precise	2.350s	267.551us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	10.040s	829.891us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	0.880s	38.284us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.120s	2.781ms	1	1	100.00
		i2c_target_nack_acqfull_addr	1.840s	2.249ms	1	1	100.00
		i2c_target_nack_txstretch	1.290s	713.350us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	3.460s	568.592us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.750s	467.228us	1	1	100.00
V2	alert_test	i2c_alert_test	0.630s	27.768us	1	1	100.00
V2	intr_test	i2c_intr_test	0.620s	24.958us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.920s	118.247us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.920s	118.247us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.690s	24.938us	1	1	100.00
		i2c_csr_rw	0.770s	21.269us	1	1	100.00
		i2c_csr_aliasing	0.990s	54.796us	1	1	100.00
		i2c_same_csr_outstanding	0.770s	67.178us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.690s	24.938us	1	1	100.00
		i2c_csr_rw	0.770s	21.269us	1	1	100.00
		i2c_csr_aliasing	0.990s	54.796us	1	1	100.00
		i2c_same_csr_outstanding	0.770s	67.178us	1	1	100.00
V2		TOTAL			33	38	86.84
V2S	tl_intg_err	i2c_tl_intg_err	1.670s	94.760us	1	1	100.00
		i2c_sec_cm	0.980s	147.164us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.670s	94.760us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	13.120s	759.030us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.650s	118.721us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	0.970s	14.902us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			42	50	84.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 3 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.34542135839289662984206942900217005474906963887158017769714497300468812766441
      Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  30243518 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  30243518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.111502605679127348187416698831935861331684698943904888108593663512017961768926
      Line 95, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @  40131073 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  40131073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.44419969733476928730653378967252734439446395982755430111492799929462449251415
      Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  14902379 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  14902379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.109089856023874166383838086925386244173436780536456326036606031948653341554933
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 519824401 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 519824401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.69560855020814009955570146726956844780870900643542428147783553399727806288265
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 118721271 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 118721271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.80862407464220397974241469874754282580538918265257698011862668442843960687319
      Line 93, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 759030268 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 759030268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.67550355931877298216281693489749148570774340966732278054915118281495936801820
      Line 82, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @  71220357 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @14514
      

• Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:

  • Test i2c_target_fifo_watermarks_tx has 1 failures.

    • 0.i2c_target_fifo_watermarks_tx.8257503774024814991618895802524080724356945457224120709136102079367202945164
      Line 118, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_fifo_watermarks_tx/latest/run.log

        Error-[CNST-CIF] Constraints inconsistency failure
        src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 845
          Constraints are inconsistent and cannot be solved.
          Please check the inconsistent constraints being printed above and rewrite
          them.