KEYMGR Simulation Results

Monday October 20 2025 16:04:01 UTC

GitHub Revision: cf33148

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 2.020s 109.882us 1 1 100.00
V1 random keymgr_random 40.000s 2.120ms 1 1 100.00
V1 csr_hw_reset keymgr_csr_hw_reset 0.960s 16.884us 1 1 100.00
V1 csr_rw keymgr_csr_rw 0.790s 34.042us 1 1 100.00
V1 csr_bit_bash keymgr_csr_bit_bash 5.210s 517.607us 1 1 100.00
V1 csr_aliasing keymgr_csr_aliasing 9.520s 386.336us 1 1 100.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 1.330s 157.680us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 0.790s 34.042us 1 1 100.00
keymgr_csr_aliasing 9.520s 386.336us 1 1 100.00
V1 TOTAL 7 7 100.00
V2 cfgen_during_op keymgr_cfg_regwen 2.230s 89.591us 1 1 100.00
V2 sideload keymgr_sideload 1.910s 45.386us 1 1 100.00
keymgr_sideload_kmac 2.100s 107.732us 1 1 100.00
keymgr_sideload_aes 36.060s 2.205ms 1 1 100.00
keymgr_sideload_otbn 2.090s 211.864us 1 1 100.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 1.790s 59.093us 1 1 100.00
V2 lc_disable keymgr_lc_disable 2.660s 303.375us 1 1 100.00
V2 kmac_error_response keymgr_kmac_rsp_err 2.070s 46.840us 1 1 100.00
V2 invalid_sw_input keymgr_sw_invalid_input 5.900s 669.432us 1 1 100.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 3.190s 186.297us 1 1 100.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 1.640s 44.221us 1 1 100.00
V2 stress_all keymgr_stress_all 11.040s 2.442ms 1 1 100.00
V2 intr_test keymgr_intr_test 0.780s 50.270us 1 1 100.00
V2 alert_test keymgr_alert_test 0.820s 21.529us 1 1 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 1.410s 570.262us 1 1 100.00
V2 tl_d_illegal_access keymgr_tl_errors 1.410s 570.262us 1 1 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 0.960s 16.884us 1 1 100.00
keymgr_csr_rw 0.790s 34.042us 1 1 100.00
keymgr_csr_aliasing 9.520s 386.336us 1 1 100.00
keymgr_same_csr_outstanding 1.260s 50.007us 1 1 100.00
V2 tl_d_partial_access keymgr_csr_hw_reset 0.960s 16.884us 1 1 100.00
keymgr_csr_rw 0.790s 34.042us 1 1 100.00
keymgr_csr_aliasing 9.520s 386.336us 1 1 100.00
keymgr_same_csr_outstanding 1.260s 50.007us 1 1 100.00
V2 TOTAL 16 16 100.00
V2S sec_cm_additional_check keymgr_sec_cm 4.580s 1.655ms 1 1 100.00
V2S tl_intg_err keymgr_sec_cm 4.580s 1.655ms 1 1 100.00
keymgr_tl_intg_err 4.570s 812.336us 1 1 100.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 2.210s 171.800us 1 1 100.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 2.210s 171.800us 1 1 100.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 2.210s 171.800us 1 1 100.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 2.210s 171.800us 1 1 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 3.870s 209.749us 1 1 100.00
V2S prim_count_check keymgr_sec_cm 4.580s 1.655ms 1 1 100.00
V2S prim_fsm_check keymgr_sec_cm 4.580s 1.655ms 1 1 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 4.570s 812.336us 1 1 100.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 2.210s 171.800us 1 1 100.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 2.230s 89.591us 1 1 100.00
V2S sec_cm_reseed_config_regwen keymgr_random 40.000s 2.120ms 1 1 100.00
keymgr_csr_rw 0.790s 34.042us 1 1 100.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 40.000s 2.120ms 1 1 100.00
keymgr_csr_rw 0.790s 34.042us 1 1 100.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 40.000s 2.120ms 1 1 100.00
keymgr_csr_rw 0.790s 34.042us 1 1 100.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 2.660s 303.375us 1 1 100.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 3.190s 186.297us 1 1 100.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 3.190s 186.297us 1 1 100.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 40.000s 2.120ms 1 1 100.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 2.270s 259.589us 1 1 100.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 4.580s 1.655ms 1 1 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 4.580s 1.655ms 1 1 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 4.580s 1.655ms 1 1 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 1.600s 140.924us 1 1 100.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 2.660s 303.375us 1 1 100.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 4.580s 1.655ms 1 1 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 4.580s 1.655ms 1 1 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 4.580s 1.655ms 1 1 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 1.600s 140.924us 1 1 100.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 1.600s 140.924us 1 1 100.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 4.580s 1.655ms 1 1 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 1.600s 140.924us 1 1 100.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 4.580s 1.655ms 1 1 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 1.600s 140.924us 1 1 100.00
V2S TOTAL 6 6 100.00
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 4.390s 174.485us 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 30 30 100.00