KEYMGR_DPE Simulation Results

Monday October 20 2025 16:04:01 UTC

GitHub Revision: cf33148

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_dpe_smoke	1.093m	23.310ms	1	1	100.00
V1	csr_hw_reset	keymgr_dpe_csr_hw_reset	1.000s	269.300us	1	1	100.00
V1	csr_rw	keymgr_dpe_csr_rw	1.230s	76.485us	1	1	100.00
V1	csr_bit_bash	keymgr_dpe_csr_bit_bash	6.750s	2.288ms	1	1	100.00
V1	csr_aliasing	keymgr_dpe_csr_aliasing	2.450s	622.481us	0	1	0.00
V1	csr_mem_rw_with_rand_reset	keymgr_dpe_csr_mem_rw_with_rand_reset	1.240s	54.706us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_dpe_csr_rw	1.230s	76.485us	1	1	100.00
		keymgr_dpe_csr_aliasing	2.450s	622.481us	0	1	0.00
V1		TOTAL			5	6	83.33
V2	intr_test	keymgr_dpe_intr_test	0.840s	14.472us	1	1	100.00
V2	alert_test	keymgr_dpe_alert_test	0.770s	101.196us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_dpe_tl_errors	1.500s	234.763us	1	1	100.00
V2	tl_d_illegal_access	keymgr_dpe_tl_errors	1.500s	234.763us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_dpe_csr_hw_reset	1.000s	269.300us	1	1	100.00
		keymgr_dpe_csr_rw	1.230s	76.485us	1	1	100.00
		keymgr_dpe_csr_aliasing	2.450s	622.481us	0	1	0.00
		keymgr_dpe_same_csr_outstanding	1.600s	32.066us	1	1	100.00
V2	tl_d_partial_access	keymgr_dpe_csr_hw_reset	1.000s	269.300us	1	1	100.00
		keymgr_dpe_csr_rw	1.230s	76.485us	1	1	100.00
		keymgr_dpe_csr_aliasing	2.450s	622.481us	0	1	0.00
		keymgr_dpe_same_csr_outstanding	1.600s	32.066us	1	1	100.00
V2		TOTAL			4	4	100.00
V2S	tl_intg_err	keymgr_dpe_sec_cm	8.270s	1.543ms	1	1	100.00
		keymgr_dpe_tl_intg_err	2.840s	196.944us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_dpe_shadow_reg_errors	1.810s	411.053us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_dpe_shadow_reg_errors	1.810s	411.053us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_dpe_shadow_reg_errors	1.810s	411.053us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_dpe_shadow_reg_errors	1.810s	411.053us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_dpe_shadow_reg_errors_with_csr_rw	3.550s	824.980us	1	1	100.00
V2S	prim_count_check	keymgr_dpe_sec_cm	8.270s	1.543ms	1	1	100.00
V2S	prim_fsm_check	keymgr_dpe_sec_cm	8.270s	1.543ms	1	1	100.00
V2S		TOTAL			4	4	100.00
		TOTAL			13	14	92.86

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: keymgr_dpe_reg_block.err_code reset value: * has 1 failures:
  • Test keymgr_dpe_csr_aliasing has 1 failures.

    • 0.keymgr_dpe_csr_aliasing.105755034836089019714134957376787834316630209878142770827969707492011559397228
      Line 78, in log /nightly/current_run/scratch/master/keymgr_dpe-sim-vcs/0.keymgr_dpe_csr_aliasing/latest/run.log

        UVM_ERROR @ 622481007 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (4 [0x4] vs 0 [0x0]) Regname: keymgr_dpe_reg_block.err_code reset value: 0x0
        UVM_INFO @ 622481007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---