KMAC/MASKED Simulation Results

Monday October 20 2025 16:04:01 UTC

GitHub Revision: cf33148

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	55.440s	5.852ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	0.980s	27.357us	1	1	100.00
V1	csr_rw	kmac_csr_rw	0.880s	21.150us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	10.610s	286.286us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.580s	209.540us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.760s	38.514us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	0.880s	21.150us	1	1	100.00
		kmac_csr_aliasing	3.580s	209.540us	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.710s	12.270us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.200s	22.444us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	11.647m	93.761ms	1	1	100.00
V2	burst_write	kmac_burst_write	3.246m	16.039ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	26.920s	2.512ms	1	1	100.00
		kmac_test_vectors_sha3_256	30.137m	75.542ms	1	1	100.00
		kmac_test_vectors_sha3_384	22.880s	1.599ms	1	1	100.00
		kmac_test_vectors_sha3_512	14.600s	4.207ms	1	1	100.00
		kmac_test_vectors_shake_128	1.550s	74.044us	0	1	0.00
		kmac_test_vectors_shake_256	30.326m	57.504ms	1	1	100.00
		kmac_test_vectors_kmac	2.440s	51.032us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.580s	290.864us	1	1	100.00
V2	sideload	kmac_sideload	30.110s	6.676ms	1	1	100.00
V2	app	kmac_app	39.950s	3.183ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	55.320s	5.716ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	27.110s	1.289ms	1	1	100.00
V2	error	kmac_error	4.278m	44.992ms	1	1	100.00
V2	key_error	kmac_key_error	7.460s	9.119ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	5.030s	526.723us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.050s	16.804us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	1.140s	65.220us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	41.160s	18.153ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.750s	143.003us	1	1	100.00
V2	stress_all	kmac_stress_all	3.138m	13.874ms	1	1	100.00
V2	intr_test	kmac_intr_test	0.860s	16.328us	1	1	100.00
V2	alert_test	kmac_alert_test	1.100s	27.154us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.850s	801.644us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.850s	801.644us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	0.980s	27.357us	1	1	100.00
		kmac_csr_rw	0.880s	21.150us	1	1	100.00
		kmac_csr_aliasing	3.580s	209.540us	1	1	100.00
		kmac_same_csr_outstanding	1.230s	27.221us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	0.980s	27.357us	1	1	100.00
		kmac_csr_rw	0.880s	21.150us	1	1	100.00
		kmac_csr_aliasing	3.580s	209.540us	1	1	100.00
		kmac_same_csr_outstanding	1.230s	27.221us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.100s	805.833us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.100s	805.833us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.100s	805.833us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.100s	805.833us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.900s	44.211us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	29.580s	13.203ms	1	1	100.00
		kmac_tl_intg_err	2.980s	104.629us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.980s	104.629us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.750s	143.003us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	55.440s	5.852ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	30.110s	6.676ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.100s	805.833us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	29.580s	13.203ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	29.580s	13.203ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	29.580s	13.203ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	55.440s	5.852ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.750s	143.003us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	29.580s	13.203ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.218m	10.511ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	55.440s	5.852ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.249m	12.197ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 1 failures:
  • Test kmac_test_vectors_shake_128 has 1 failures.

    • 0.kmac_test_vectors_shake_128.22413109382614459038858763722534164857057861527004109220288538938709570413023
      Line 75, in log /nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_128/latest/run.log

        UVM_ERROR @  74044373 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
        UVM_INFO @  74044373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---