KMAC/UNMASKED Simulation Results

Monday October 20 2025 16:04:01 UTC

GitHub Revision: cf33148

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	28.560s	1.605ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	0.900s	61.749us	1	1	100.00
V1	csr_rw	kmac_csr_rw	0.790s	63.421us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	7.080s	732.682us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	2.930s	148.596us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	1.260s	165.768us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	0.790s	63.421us	1	1	100.00
		kmac_csr_aliasing	2.930s	148.596us	1	1	100.00
V1	mem_walk	kmac_mem_walk	0.650s	16.748us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.130s	44.646us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	17.550m	31.524ms	1	1	100.00
V2	burst_write	kmac_burst_write	3.929m	14.080ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	30.240s	3.718ms	1	1	100.00
		kmac_test_vectors_sha3_256	28.886m	168.666ms	1	1	100.00
		kmac_test_vectors_sha3_384	16.040s	412.362us	1	1	100.00
		kmac_test_vectors_sha3_512	9.256m	15.583ms	1	1	100.00
		kmac_test_vectors_shake_128	2.268m	48.620ms	1	1	100.00
		kmac_test_vectors_shake_256	4.143m	40.065ms	1	1	100.00
		kmac_test_vectors_kmac	1.550s	211.001us	1	1	100.00
		kmac_test_vectors_kmac_xof	1.620s	71.141us	1	1	100.00
V2	sideload	kmac_sideload	3.124m	9.303ms	1	1	100.00
V2	app	kmac_app	2.707m	18.878ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	28.440s	8.796ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	3.205m	39.847ms	1	1	100.00
V2	error	kmac_error	2.652m	2.893ms	1	1	100.00
V2	key_error	kmac_key_error	4.150s	7.285ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.860s	296.699us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	6.320s	671.089us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	27.990s	2.081ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	35.200s	41.399ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	1.420s	310.180us	1	1	100.00
V2	stress_all	kmac_stress_all	10.517m	29.534ms	1	1	100.00
V2	intr_test	kmac_intr_test	0.810s	25.852us	1	1	100.00
V2	alert_test	kmac_alert_test	0.770s	42.950us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	1.750s	92.988us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	1.750s	92.988us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	0.900s	61.749us	1	1	100.00
		kmac_csr_rw	0.790s	63.421us	1	1	100.00
		kmac_csr_aliasing	2.930s	148.596us	1	1	100.00
		kmac_same_csr_outstanding	1.300s	70.351us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	0.900s	61.749us	1	1	100.00
		kmac_csr_rw	0.790s	63.421us	1	1	100.00
		kmac_csr_aliasing	2.930s	148.596us	1	1	100.00
		kmac_same_csr_outstanding	1.300s	70.351us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.220s	59.562us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.220s	59.562us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.220s	59.562us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.220s	59.562us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.900s	51.687us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	24.930s	14.782ms	1	1	100.00
		kmac_tl_intg_err	1.710s	135.048us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.710s	135.048us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.420s	310.180us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	28.560s	1.605ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.124m	9.303ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.220s	59.562us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	24.930s	14.782ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	24.930s	14.782ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	24.930s	14.782ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	28.560s	1.605ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.420s	310.180us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	24.930s	14.782ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.362m	13.203ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	28.560s	1.605ms	1	1	100.00
V2S		TOTAL			5	5	100.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	40.060s	2.404ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	40	97.50

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:840) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.107387405930329374828895930658815236663890696413016404250254641957765346085779
      Line 212, in log /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2404333809 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
        UVM_INFO @ 2404333809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---