MBX Simulation Results

Monday October 20 2025 16:04:01 UTC

GitHub Revision: cf33148

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	mbx_smoke	mbx_smoke	1.350m	16.011ms	1	1	100.00
V1	csr_hw_reset	mbx_csr_hw_reset	1.000s	48.736us	1	1	100.00
V1	csr_rw	mbx_csr_rw	2.000s	39.085us	1	1	100.00
V1	csr_bit_bash	mbx_csr_bit_bash	3.000s	75.002us	1	1	100.00
V1	csr_aliasing	mbx_csr_aliasing	2.000s	57.583us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	mbx_csr_mem_rw_with_rand_reset	2.000s	31.285us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	mbx_csr_rw	2.000s	39.085us	1	1	100.00
		mbx_csr_aliasing	2.000s	57.583us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	mbx_stress	mbx_stress	13.000s	8.180ms	0	1	0.00
V2	mbx_max_activity	mbx_stress_zero_delays	10.000s	197.451us	0	1	0.00
V2	mbx_imbx_oob	mbx_imbx_oob	7.000s	153.545us	0	1	0.00
V2	mbx_doe_intr_msg	mbx_doe_intr_msg	13.000s	2.655ms	1	1	100.00
V2	alert_test	mbx_alert_test	4.000s	47.261us	1	1	100.00
V2	intr_test	mbx_intr_test	2.000s	31.023us	1	1	100.00
V2	tl_d_oob_addr_access	mbx_tl_errors	5.000s	1.019ms	1	1	100.00
V2	tl_d_illegal_access	mbx_tl_errors	5.000s	1.019ms	1	1	100.00
V2	tl_d_outstanding_access	mbx_csr_hw_reset	1.000s	48.736us	1	1	100.00
		mbx_csr_rw	2.000s	39.085us	1	1	100.00
		mbx_csr_aliasing	2.000s	57.583us	1	1	100.00
		mbx_same_csr_outstanding	1.000s	71.636us	1	1	100.00
V2	tl_d_partial_access	mbx_csr_hw_reset	1.000s	48.736us	1	1	100.00
		mbx_csr_rw	2.000s	39.085us	1	1	100.00
		mbx_csr_aliasing	2.000s	57.583us	1	1	100.00
		mbx_same_csr_outstanding	1.000s	71.636us	1	1	100.00
V2		TOTAL			5	8	62.50
V2S	tl_intg_err	mbx_tl_intg_err	3.000s	305.563us	1	1	100.00
		mbx_sec_cm	3.000s	11.494us	1	1	100.00
V2S		TOTAL			2	2	100.00
		TOTAL			13	16	81.25

Failure Buckets

• UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register has 3 failures:

  • Test mbx_stress has 1 failures.

    • 0.mbx_stress.108572720215995419328955538483178974902576937781686000563767637510905486900882
      Line 181, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress/latest/run.log

        UVM_ERROR @ 8179978973 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
        UVM_INFO @ 8179978973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test mbx_stress_zero_delays has 1 failures.

    • 0.mbx_stress_zero_delays.56640928751960293386947039863690954063056318437948581347477535754404966796222
      Line 524, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress_zero_delays/latest/run.log

        UVM_ERROR @ 197450856 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
        UVM_INFO @ 197450856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test mbx_imbx_oob has 1 failures.

    • 0.mbx_imbx_oob.21407883808463236255635715909687851352127799100744371031030572817321139835047
      Line 96, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_imbx_oob/latest/run.log

        UVM_ERROR @ 153544853 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
        UVM_INFO @ 153544853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---