OTBN Simulation Results

Monday October 20 2025 16:04:01 UTC

GitHub Revision: cf33148

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 8.000s 159.044us 0 1 0.00
V1 single_binary otbn_single 7.000s 27.444us 0 1 0.00
V1 csr_hw_reset otbn_csr_hw_reset 4.000s 80.983us 1 1 100.00
V1 csr_rw otbn_csr_rw 4.000s 13.957us 1 1 100.00
V1 csr_bit_bash otbn_csr_bit_bash 5.000s 113.194us 1 1 100.00
V1 csr_aliasing otbn_csr_aliasing 4.000s 44.245us 1 1 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 4.000s 340.257us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 4.000s 13.957us 1 1 100.00
otbn_csr_aliasing 4.000s 44.245us 1 1 100.00
V1 mem_walk otbn_mem_walk 26.000s 1.198ms 1 1 100.00
V1 mem_partial_access otbn_mem_partial_access 9.000s 854.829us 1 1 100.00
V1 TOTAL 7 9 77.78
V2 reset_recovery otbn_reset 14.000s 56.683us 0 1 0.00
V2 multi_error otbn_multi_err 47.000s 154.011us 0 1 0.00
V2 back_to_back otbn_multi 30.000s 192.009us 0 1 0.00
V2 stress_all otbn_stress_all 29.000s 331.210us 0 1 0.00
V2 lc_escalation otbn_escalate 6.000s 32.428us 1 1 100.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 8.000s 25.087us 0 1 0.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 9.000s 29.341us 0 1 0.00
V2 alert_test otbn_alert_test 3.000s 91.263us 1 1 100.00
V2 intr_test otbn_intr_test 3.000s 14.536us 1 1 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 5.000s 224.488us 1 1 100.00
V2 tl_d_illegal_access otbn_tl_errors 5.000s 224.488us 1 1 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 4.000s 80.983us 1 1 100.00
otbn_csr_rw 4.000s 13.957us 1 1 100.00
otbn_csr_aliasing 4.000s 44.245us 1 1 100.00
otbn_same_csr_outstanding 3.000s 44.243us 1 1 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 4.000s 80.983us 1 1 100.00
otbn_csr_rw 4.000s 13.957us 1 1 100.00
otbn_csr_aliasing 4.000s 44.245us 1 1 100.00
otbn_same_csr_outstanding 3.000s 44.243us 1 1 100.00
V2 TOTAL 5 11 45.45
V2S mem_integrity otbn_imem_err 10.000s 77.297us 0 1 0.00
otbn_dmem_err 7.000s 19.064us 0 1 0.00
V2S internal_integrity otbn_alu_bignum_mod_err 15.000s 49.433us 0 1 0.00
otbn_controller_ispr_rdata_err 8.000s 53.781us 0 1 0.00
otbn_mac_bignum_acc_err 8.000s 213.366us 0 1 0.00
otbn_urnd_err 7.000s 18.626us 0 1 0.00
V2S illegal_bus_access otbn_illegal_mem_acc 4.000s 27.519us 1 1 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 7.000s 20.925us 0 1 0.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 6.000s 36.921us 1 1 100.00
V2S tl_intg_err otbn_sec_cm 6.567m 2.360ms 1 1 100.00
otbn_tl_intg_err 15.000s 112.949us 1 1 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 21.000s 198.027us 1 1 100.00
V2S prim_fsm_check otbn_sec_cm 6.567m 2.360ms 1 1 100.00
V2S prim_count_check otbn_sec_cm 6.567m 2.360ms 1 1 100.00
V2S sec_cm_mem_scramble otbn_smoke 8.000s 159.044us 0 1 0.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 7.000s 19.064us 0 1 0.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 10.000s 77.297us 0 1 0.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 15.000s 112.949us 1 1 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 6.000s 32.428us 1 1 100.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 10.000s 77.297us 0 1 0.00
otbn_dmem_err 7.000s 19.064us 0 1 0.00
otbn_zero_state_err_urnd 8.000s 25.087us 0 1 0.00
otbn_illegal_mem_acc 4.000s 27.519us 1 1 100.00
otbn_sec_cm 6.567m 2.360ms 1 1 100.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 6.567m 2.360ms 1 1 100.00
V2S sec_cm_scramble_key_sideload otbn_single 7.000s 27.444us 0 1 0.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 10.000s 77.297us 0 1 0.00
otbn_dmem_err 7.000s 19.064us 0 1 0.00
otbn_zero_state_err_urnd 8.000s 25.087us 0 1 0.00
otbn_illegal_mem_acc 4.000s 27.519us 1 1 100.00
otbn_sec_cm 6.567m 2.360ms 1 1 100.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 6.567m 2.360ms 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 6.000s 32.428us 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 10.000s 77.297us 0 1 0.00
otbn_dmem_err 7.000s 19.064us 0 1 0.00
otbn_zero_state_err_urnd 8.000s 25.087us 0 1 0.00
otbn_illegal_mem_acc 4.000s 27.519us 1 1 100.00
otbn_sec_cm 6.567m 2.360ms 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 6.567m 2.360ms 1 1 100.00
V2S sec_cm_data_reg_sw_sca otbn_single 7.000s 27.444us 0 1 0.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 6.000s 41.292us 0 1 0.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 5.000s 74.790us 1 1 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 50.000s 802.677us 0 1 0.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 50.000s 802.677us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 10.000s 59.558us 0 1 0.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 6.567m 2.360ms 1 1 100.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 6.567m 2.360ms 1 1 100.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 12.000s 208.122us 0 1 0.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 6.567m 2.360ms 1 1 100.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 6.567m 2.360ms 1 1 100.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 7.000s 23.636us 0 1 0.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 7.000s 23.636us 0 1 0.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 6.000s 26.650us 1 1 100.00
V2S sec_cm_data_mem_sec_wipe otbn_single 7.000s 27.444us 0 1 0.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 7.000s 27.444us 0 1 0.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 7.000s 27.444us 0 1 0.00
V2S sec_cm_write_mem_integrity otbn_multi 30.000s 192.009us 0 1 0.00
V2S sec_cm_ctrl_flow_count otbn_single 7.000s 27.444us 0 1 0.00
V2S sec_cm_ctrl_flow_sca otbn_single 7.000s 27.444us 0 1 0.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 10.000s 37.584us 0 1 0.00
V2S sec_cm_key_sideload otbn_single 7.000s 27.444us 0 1 0.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 6.567m 2.360ms 1 1 100.00
V2S TOTAL 7 20 35.00
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 1.150m 2.878ms 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 19 41 46.34

Failure Buckets