ROM_CTRL/32KB Simulation Results

Monday October 20 2025 16:04:01 UTC

GitHub Revision: cf33148

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	4.550s	995.250us	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	6.420s	203.469us	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	3.030s	373.612us	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	3.770s	556.464us	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	3.820s	128.420us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	3.840s	464.258us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	3.030s	373.612us	1	1	100.00
		rom_ctrl_csr_aliasing	3.820s	128.420us	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	4.430s	200.644us	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	4.410s	384.755us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	5.190s	138.216us	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	18.840s	2.158ms	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	9.810s	1.045ms	1	1	100.00
V2	alert_test	rom_ctrl_alert_test	4.560s	169.741us	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	6.510s	538.504us	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	6.510s	538.504us	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	6.420s	203.469us	1	1	100.00
		rom_ctrl_csr_rw	3.030s	373.612us	1	1	100.00
		rom_ctrl_csr_aliasing	3.820s	128.420us	1	1	100.00
		rom_ctrl_same_csr_outstanding	5.280s	168.600us	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	6.420s	203.469us	1	1	100.00
		rom_ctrl_csr_rw	3.030s	373.612us	1	1	100.00
		rom_ctrl_csr_aliasing	3.820s	128.420us	1	1	100.00
		rom_ctrl_same_csr_outstanding	5.280s	168.600us	1	1	100.00
V2		TOTAL			6	6	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	1.048m	8.642ms	1	1	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	14.020s	7.526ms	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.329m	945.168us	0	1	0.00
		rom_ctrl_tl_intg_err	46.200s	453.502us	1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.329m	945.168us	0	1	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	3.329m	945.168us	0	1	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.048m	8.642ms	1	1	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.048m	8.642ms	1	1	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.048m	8.642ms	1	1	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.048m	8.642ms	1	1	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.048m	8.642ms	1	1	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.329m	945.168us	0	1	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.329m	945.168us	0	1	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	4.550s	995.250us	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	4.550s	995.250us	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	4.550s	995.250us	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	46.200s	453.502us	1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.048m	8.642ms	1	1	100.00
		rom_ctrl_kmac_err_chk	9.810s	1.045ms	1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	1.048m	8.642ms	1	1	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.048m	8.642ms	1	1	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	1.048m	8.642ms	1	1	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	14.020s	7.526ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.329m	945.168us	0	1	0.00
V2S		TOTAL			3	4	75.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	5.033m	16.150ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			18	19	94.74

Failure Buckets

• Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' has 1 failures:
  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.16329311022422249778924283709949531330600165225276186614160431223406006793133
      Line 186, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 26274985ps failed at 26274985ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        Starting assertion attempts at time 30889830ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
        Starting assertion attempts at time 30889830ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))