RV_TIMER Simulation Results

Monday October 20 2025 16:04:01 UTC

GitHub Revision: cf33148

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	0.930s	425.533us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.620s	14.283us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.710s	15.404us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	1.630s	129.481us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.010s	42.281us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	0.860s	18.858us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.710s	15.404us	1	1	100.00
		rv_timer_csr_aliasing	1.010s	42.281us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	0.940s	231.081us	0	1	0.00
V2	disabled	rv_timer_disabled	0.960s	987.186us	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	5.364m	468.117ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	5.364m	468.117ms	1	1	100.00
V2	stress	rv_timer_stress_all	4.710s	3.175ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.570s	43.315us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.540s	25.551us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.310s	164.065us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.310s	164.065us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.620s	14.283us	1	1	100.00
		rv_timer_csr_rw	0.710s	15.404us	1	1	100.00
		rv_timer_csr_aliasing	1.010s	42.281us	1	1	100.00
		rv_timer_same_csr_outstanding	0.940s	78.588us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.620s	14.283us	1	1	100.00
		rv_timer_csr_rw	0.710s	15.404us	1	1	100.00
		rv_timer_csr_aliasing	1.010s	42.281us	1	1	100.00
		rv_timer_same_csr_outstanding	0.940s	78.588us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	rv_timer_sec_cm	0.940s	210.688us	1	1	100.00
		rv_timer_tl_intg_err	1.210s	124.764us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.210s	124.764us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	0.790s	119.059us	0	1	0.00
V3	max_value	rv_timer_max	0.840s	472.701us	0	1	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	11.400s	1.630ms	1	1	100.00
V3		TOTAL			1	3	33.33
		TOTAL			16	19	84.21

Failure Buckets

• UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 2 failures:

  • Test rv_timer_min has 1 failures.

    • 0.rv_timer_min.41532477014705359041308279442132503402994431633961093010933607644441368828509
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log

        UVM_FATAL @ 119059225 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x43fddb04) == 0x1
        UVM_INFO @ 119059225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_timer_random_reset has 1 failures.

    • 0.rv_timer_random_reset.39879588578429188340772307396918610584118400514566434517890559557941256941320
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log

        UVM_FATAL @ 231080890 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x56747304) == 0x1
        UVM_INFO @ 231080890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:

  • Test rv_timer_max has 1 failures.

    • 0.rv_timer_max.115474147028874882583841267806797401800937951552292694865442113644280040348792
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log

        UVM_ERROR @ 472700895 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 472700895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---