SPI_DEVICE/1R1W Simulation Results

Monday October 20 2025 16:04:01 UTC

GitHub Revision: cf33148

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	2.530s	164.887us	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.080s	107.150us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.530s	29.426us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	25.680s	11.782ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	5.840s	332.025us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.940s	58.349us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.530s	29.426us	1	1	100.00
		spi_device_csr_aliasing	5.840s	332.025us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.700s	10.646us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.240s	17.943us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.900s	20.682us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.710s	2.114us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.680s	3.393us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	0.860s	12.740us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	0.860s	12.740us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	8.480s	3.803ms	1	1	100.00
		spi_device_tpm_sts_read	1.070s	22.918us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	15.800s	2.076ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	6.320s	2.536ms	1	1	100.00
		spi_device_flash_all	48.500s	14.164ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	4.240s	4.647ms	1	1	100.00
		spi_device_flash_all	48.500s	14.164ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	4.240s	4.647ms	1	1	100.00
		spi_device_flash_all	48.500s	14.164ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	48.500s	14.164ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	2.480s	194.114us	1	1	100.00
		spi_device_flash_all	48.500s	14.164ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	2.480s	194.114us	1	1	100.00
		spi_device_flash_all	48.500s	14.164ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	2.480s	194.114us	1	1	100.00
		spi_device_flash_all	48.500s	14.164ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	2.480s	194.114us	1	1	100.00
		spi_device_flash_all	48.500s	14.164ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	2.480s	194.114us	1	1	100.00
		spi_device_flash_all	48.500s	14.164ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	3.910s	13.350ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	6.710s	664.110us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	6.710s	664.110us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	6.710s	664.110us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	6.080s	307.964us	1	1	100.00
		spi_device_read_buffer_direct	6.450s	1.414ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	6.710s	664.110us	1	1	100.00
		spi_device_flash_all	48.500s	14.164ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	48.500s	14.164ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	48.500s	14.164ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	8.860s	1.305ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	8.860s	1.305ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	2.530s	164.887us	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	2.158m	50.689ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.260s	61.804us	1	1	100.00
V2	alert_test	spi_device_alert_test	0.870s	10.984us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.780s	22.082us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	1.940s	60.501us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	1.940s	60.501us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.080s	107.150us	1	1	100.00
		spi_device_csr_rw	1.530s	29.426us	1	1	100.00
		spi_device_csr_aliasing	5.840s	332.025us	1	1	100.00
		spi_device_same_csr_outstanding	3.220s	318.395us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.080s	107.150us	1	1	100.00
		spi_device_csr_rw	1.530s	29.426us	1	1	100.00
		spi_device_csr_aliasing	5.840s	332.025us	1	1	100.00
		spi_device_same_csr_outstanding	3.220s	318.395us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.210s	1.130ms	1	1	100.00
		spi_device_tl_intg_err	10.410s	935.065us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	10.410s	935.065us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	16.850s	2.686ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.8416043078603030644657041274531319028971800753484162146602515085535548512357
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1926304 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[76])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1926304 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1926304 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[972])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.3622166854622147789820558318676624032740917094016703201280383864167275808130
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @    830967 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x230270 [1000110000001001110000] vs 0x0 [0])
        UVM_ERROR @    909967 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb867ad [101110000110011110101101] vs 0x0 [0])
        UVM_ERROR @    956967 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa0d8a9 [101000001101100010101001] vs 0x0 [0])
        UVM_ERROR @   1009967 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x8e3ecd [100011100011111011001101] vs 0x0 [0])
        UVM_ERROR @   1061967 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xad47cb [101011010100011111001011] vs 0x0 [0])