SPI_HOST Simulation Results

Monday October 20 2025 16:04:01 UTC

GitHub Revision: cf33148

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	11.000s	1.067ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	1.000s	25.779us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	2.000s	79.005us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	2.000s	111.696us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	1.000s	20.497us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	67.993us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	2.000s	79.005us	1	1	100.00
		spi_host_csr_aliasing	1.000s	20.497us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	2.000s	22.539us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	23.515us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	1.000s	36.885us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	1.000s	38.994us	1	1	100.00
		spi_host_error_cmd	1.000s	23.027us	1	1	100.00
		spi_host_event	3.000s	696.161us	1	1	100.00
V2	clock_rate	spi_host_speed	2.000s	47.855us	1	1	100.00
V2	speed	spi_host_speed	2.000s	47.855us	1	1	100.00
V2	chip_select_timing	spi_host_speed	2.000s	47.855us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	3.000s	90.235us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	1.000s	118.314us	1	1	100.00
V2	cpol_cpha	spi_host_speed	2.000s	47.855us	1	1	100.00
V2	full_cycle	spi_host_speed	2.000s	47.855us	1	1	100.00
V2	duplex	spi_host_smoke	11.000s	1.067ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	11.000s	1.067ms	1	1	100.00
V2	stress_all	spi_host_stress_all	3.750m	1.000s	0	1	0.00
V2	spien	spi_host_spien	3.000s	317.825us	1	1	100.00
V2	stall	spi_host_status_stall	19.000s	2.724ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	2.000s	101.093us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	1.000s	38.994us	1	1	100.00
V2	alert_test	spi_host_alert_test	1.000s	40.524us	1	1	100.00
V2	intr_test	spi_host_intr_test	1.000s	52.274us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	2.000s	388.295us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	2.000s	388.295us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	1.000s	25.779us	1	1	100.00
		spi_host_csr_rw	2.000s	79.005us	1	1	100.00
		spi_host_csr_aliasing	1.000s	20.497us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	75.686us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	1.000s	25.779us	1	1	100.00
		spi_host_csr_rw	2.000s	79.005us	1	1	100.00
		spi_host_csr_aliasing	1.000s	20.497us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	75.686us	1	1	100.00
V2		TOTAL			14	15	93.33
V2S	tl_intg_err	spi_host_tl_intg_err	1.000s	240.086us	1	1	100.00
		spi_host_sec_cm	1.000s	135.757us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	1.000s	240.086us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	4.817m	39.490ms	1	1	100.00
		TOTAL			25	26	96.15

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test spi_host_stress_all has 1 failures.

    • 0.spi_host_stress_all.57863909096004660685601646019133841304703556705291041886632959230167487123130
      Line 126, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_stress_all/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---