SRAM_CTRL/MAIN Simulation Results

Monday October 20 2025 16:04:01 UTC

GitHub Revision: cf33148

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	10.350s	2.808ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.960s	17.005us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.670s	10.796us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.880s	125.725us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	0.880s	123.181us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.810s	726.110us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.670s	10.796us	1	1	100.00
		sram_ctrl_csr_aliasing	0.880s	123.181us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.492m	2.062ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.495m	1.625ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	16.159m	52.502ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.446m	6.446ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	18.827m	134.554ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	12.299m	52.288ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	36.250s	15.572ms	1	1	100.00
V2	executable	sram_ctrl_executable	31.770s	2.970ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	6.720s	763.428us	1	1	100.00
		sram_ctrl_partial_access_b2b	6.026m	82.340ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	31.600s	765.378us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	55.200s	3.088ms	1	1	100.00
		sram_ctrl_throughput_w_readback	33.150s	3.505ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	3.025m	11.926ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.610s	703.430us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	24.354m	52.171ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.820s	15.018us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	1.890s	67.759us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	1.890s	67.759us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.960s	17.005us	1	1	100.00
		sram_ctrl_csr_rw	0.670s	10.796us	1	1	100.00
		sram_ctrl_csr_aliasing	0.880s	123.181us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.870s	80.903us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.960s	17.005us	1	1	100.00
		sram_ctrl_csr_rw	0.670s	10.796us	1	1	100.00
		sram_ctrl_csr_aliasing	0.880s	123.181us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.870s	80.903us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	28.990s	7.061ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.840s	9.911us	0	1	0.00
		sram_ctrl_tl_intg_err	2.950s	568.847us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.840s	9.911us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.950s	568.847us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	3.025m	11.926ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	3.025m	11.926ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.670s	10.796us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	31.770s	2.970ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	31.770s	2.970ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	31.770s	2.970ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	36.250s	15.572ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	6.090s	6.074ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	28.990s	7.061ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.470s	695.530us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	10.350s	2.808ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	10.350s	2.808ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	31.770s	2.970ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.840s	9.911us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	36.250s	15.572ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.840s	9.911us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.840s	9.911us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	10.350s	2.808ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.840s	9.911us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	59.680s	16.237ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.62753692489360913369682838821928233463099906520831655442156374456094875616696
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   9910621 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   9910621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---