UART Simulation Results

Monday October 20 2025 16:04:01 UTC

GitHub Revision: cf33148

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.370s	255.752us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.690s	22.351us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.790s	52.641us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.420s	112.227us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.750s	35.694us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.770s	22.512us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.790s	52.641us	1	1	100.00
		uart_csr_aliasing	0.750s	35.694us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	14.480s	37.644ms	1	1	100.00
V2	parity	uart_smoke	1.370s	255.752us	1	1	100.00
		uart_tx_rx	14.480s	37.644ms	1	1	100.00
V2	parity_error	uart_intr	27.460s	19.362ms	1	1	100.00
		uart_rx_parity_err	12.480s	28.268ms	1	1	100.00
V2	watermark	uart_tx_rx	14.480s	37.644ms	1	1	100.00
		uart_intr	27.460s	19.362ms	1	1	100.00
V2	fifo_full	uart_fifo_full	2.672m	91.021ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	1.829m	95.013ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	2.071m	116.961ms	1	1	100.00
V2	rx_frame_err	uart_intr	27.460s	19.362ms	1	1	100.00
V2	rx_break_err	uart_intr	27.460s	19.362ms	1	1	100.00
V2	rx_timeout	uart_intr	27.460s	19.362ms	1	1	100.00
V2	perf	uart_perf	2.504m	14.987ms	1	1	100.00
V2	sys_loopback	uart_loopback	3.820s	2.270ms	1	1	100.00
V2	line_loopback	uart_loopback	3.820s	2.270ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	1.030s	3.664ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	3.720s	3.848ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	6.720s	8.616ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	4.550s	3.060ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	2.096m	212.355ms	1	1	100.00
V2	stress_all	uart_stress_all	5.404m	342.938ms	1	1	100.00
V2	alert_test	uart_alert_test	0.630s	20.536us	1	1	100.00
V2	intr_test	uart_intr_test	0.620s	15.265us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.470s	226.389us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.470s	226.389us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.690s	22.351us	1	1	100.00
		uart_csr_rw	0.790s	52.641us	1	1	100.00
		uart_csr_aliasing	0.750s	35.694us	1	1	100.00
		uart_same_csr_outstanding	0.710s	84.738us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.690s	22.351us	1	1	100.00
		uart_csr_rw	0.790s	52.641us	1	1	100.00
		uart_csr_aliasing	0.750s	35.694us	1	1	100.00
		uart_same_csr_outstanding	0.710s	84.738us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	1.030s	295.494us	1	1	100.00
		uart_tl_intg_err	0.880s	193.149us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	0.880s	193.149us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	16.120s	15.271ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.92781063979077031145589705845807585496049136413718391887792195231596315881610
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 987391145 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 6,                                 clk_pulses: 0
        UVM_ERROR @ 987516145 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 987641145 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 191 [0xbf]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 987766145 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 987891145 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 254 [0xfe]) reg name: uart_reg_block.rdata