CHIP Simulation Results

Monday October 20 2025 16:04:01 UTC

GitHub Revision: `cf33148`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	19.442s		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	19.442s		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	12.224s		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	12.715s		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	12.971s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	6.405m	4.772ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	6.405m	4.772ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	6.405m	4.772ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	30.750s	10.160us	0	1	0.00
		chip_sw_example_manufacturer	2.496m		0	1	0.00
		chip_sw_example_concurrency	4.271m	4.063ms	1	1	100.00
		chip_sw_uart_smoketest_signed	12.674s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	8.930s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	9.640s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	9.640s		0	1	0.00
V1	xbar_smoke	xbar_smoke	8.940s	11.906us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	13.859s		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	13.834m	9.340ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	5.875m	5.371ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	11.735s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	15.428s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	11.098s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	11.506s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.970s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.970s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	1.109m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	38.977s		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	1.487m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	1.487m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.342m	3.980ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	3.135m	2.935ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.682m	14.003ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.795s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	12.101s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	18.385m	31.641ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	6.761m	6.773ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	25.899m	18.019ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	25.899m	18.019ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	12.085s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.378m	3.545ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.378m	3.545ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	8.698m	18.019ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.843m	4.403ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	7.048m	5.341ms	1	1	100.00
		chip_sw_aes_idle	4.056m	3.815ms	1	1	100.00
		chip_sw_hmac_enc_idle	5.421m	6.128ms	1	1	100.00
		chip_sw_kmac_idle	4.071m	4.947ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	12.321m	12.027ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	12.075m	12.027ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	13.527m	12.027ms	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	11.767m	12.027ms	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	12.159s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.214s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.600s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.897s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.461s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.688s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.803s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	12.159s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.214s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.600s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.897s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.461s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.688s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.803s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	12.695s		0	1	0.00
		chip_sw_aes_enc_jitter_en	43.960s	10.400us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	39.750s	10.140us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	45.770s	10.220us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	43.110s	10.160us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.826s		0	1	0.00
		chip_sw_clkmgr_jitter	3.112m	3.705ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.823m	5.551ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	13.558s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	36.210s	10.260us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	35.880s	10.200us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	36.190s	10.120us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	38.200s	10.160us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	43.530s	10.400us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	11.553s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	13.256s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	13.428s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	12.242s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	22.396m	14.037ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	10.420m	10.992ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	4.378m	3.545ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	13.078s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	10.420m	10.992ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	13.227s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	11.319s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	12.941s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	11.274s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	11.963s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	22.396m	14.037ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.682m	14.003ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	25.443m	20.018ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	7.542m	8.961ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	8.502m	6.554ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.207m	4.070ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	22.396m	14.037ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	11.390s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	13.234s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	22.396m	14.037ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	12.293s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	8.502m	6.554ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	14.439s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	12.537s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	13.934s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	14.888s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	12.943s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	13.767s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	13.234s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	11.755s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	13.960s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	11.755s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	11.755s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	11.755s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	7.323m	6.790ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	14.928s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	12.781s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	13.570s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	12.492s		0	1	0.00
		chip_sw_lc_ctrl_transition	11.755s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	8.309m	8.791ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	10.420m	12.167ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	11.743s		0	1	0.00
		chip_prim_tl_access	4.080m	6.348ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	12.159s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.214s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.600s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.897s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.461s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.688s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.803s		0	1	0.00
		chip_rv_dm_lc_disabled	18.385m	31.641ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.668m	3.956ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	43.960s	10.400us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.544m	5.423ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.056m	3.815ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.119m	4.642ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	39.750s	10.140us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.421m	6.128ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.644m	4.985ms	1	1	100.00
		chip_sw_kmac_mode_kmac	4.849m	4.328ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	43.110s	10.160us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	8.309m	8.791ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	11.755s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	43.760s	10.300us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.901m	4.520ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.071m	4.947ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.289s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.289s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	13.834s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.361m	4.062ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	12.735s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	8.309m	8.791ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	45.770s	10.220us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	14.766s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	12.695s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	7.048m	5.341ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	7.048m	5.341ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	7.048m	5.341ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	8.224m	5.896ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	10.420m	12.167ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	10.420m	12.167ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	8.591m	7.610ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.826s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	11.743s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	22.396m	14.037ms	1	1	100.00
		chip_sw_data_integrity_escalation	1.487m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	11.755s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	8.224m	5.896ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	8.309m	8.791ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.591m	7.610ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.003m	4.590ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	8.224m	5.896ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	8.309m	8.791ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.591m	7.610ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.003m	4.590ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	11.755s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	12.756s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	13.960s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	14.928s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	12.781s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	13.570s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	12.492s		0	1	0.00
		chip_sw_lc_ctrl_transition	11.755s		0	1	0.00
		chip_prim_tl_access	4.080m	6.348ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	4.080m	6.348ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	11.647s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	12.195s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	13.256s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	12.695s		0	1	0.00
		chip_sw_aes_enc_jitter_en	43.960s	10.400us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	39.750s	10.140us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	45.770s	10.220us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	43.110s	10.160us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.826s		0	1	0.00
		chip_sw_clkmgr_jitter	3.112m	3.705ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	7.308m	8.068ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	7.308m	8.068ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	5.912m	5.814ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	5.042m	4.820ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	3.669m	4.013ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.344m	7.049ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	6.231m	5.131ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.845m	5.036ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	4.003m	4.590ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	25.443m	20.018ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	25.443m	20.018ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	4.369m	5.689ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.888m	3.371ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.564m	4.024ms	1	1	100.00
		chip_sw_csrng_smoketest	3.947m	4.357ms	1	1	100.00
		chip_sw_gpio_smoketest	3.818m	3.693ms	1	1	100.00
		chip_sw_hmac_smoketest	4.370m	4.730ms	1	1	100.00
		chip_sw_kmac_smoketest	4.364m	4.870ms	1	1	100.00
		chip_sw_otbn_smoketest	5.129m	4.497ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.538m	5.633ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.055m	3.409ms	1	1	100.00
		chip_sw_rv_timer_smoketest	5.345m	6.311ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.304m	3.262ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.980m	4.882ms	1	1	100.00
		chip_sw_uart_smoketest	3.721m	3.646ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	11.631s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	12.674s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	13.859s		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	12.411s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.599m	4.662ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.837m	4.333ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.515m	6.051ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.333m	4.729ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	13.178s		0	1	0.00
		chip_rv_dm_lc_disabled	18.385m	31.641ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	13.264s		0	1	0.00
		chip_sw_lc_walkthrough_prod	12.183s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	11.701s		0	1	0.00
		chip_sw_lc_walkthrough_rma	11.625s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	13.178s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	11.306s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	11.742s		0	1	0.00
		rom_volatile_raw_unlock	11.594s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	12.001s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	12.172s		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	13.085s		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.982m	3.076ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.982m	3.076ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	9.640s		0	1	0.00
		chip_same_csr_outstanding	9.030s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	9.640s		0	1	0.00
		chip_same_csr_outstanding	9.030s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	2.994m	407.675us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	9.580s	12.691us	1	1	100.00
		xbar_smoke_large_delays	5.394m	2.734ms	1	1	100.00
		xbar_smoke_slow_rsp	5.704m	2.014ms	1	1	100.00
		xbar_random_zero_delays	13.020s	14.436us	1	1	100.00
		xbar_random_large_delays	13.674m	6.944ms	1	1	100.00
		xbar_random_slow_rsp	4.077m	1.425ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	24.110s	17.025us	1	1	100.00
		xbar_error_and_unmapped_addr	27.510s	21.018us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	1.649m	290.803us	1	1	100.00
		xbar_error_and_unmapped_addr	27.510s	21.018us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	5.564m	786.221us	1	1	100.00
		xbar_access_same_device_slow_rsp	23.589m	8.474ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	2.304m	390.180us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	16.637m	2.363ms	1	1	100.00
		xbar_stress_all_with_error	9.157m	1.552ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	26.014m	804.923us	1	1	100.00
		xbar_stress_all_with_reset_error	27.293m	1.451ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	13.798s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	11.872s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	15.201s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	12.510s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	13.245s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	11.819s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	13.259s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	12.605s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	13.328s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	11.753s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	13.143s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	11.967s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	12.271s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	57.207s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	1.188m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	1.015m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	53.433s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	57.384s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	46.115s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	43.785s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	36.576s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	51.346s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	43.621s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	30.595s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	36.429s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	31.216s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	28.869s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	31.578s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	15.796s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	16.394s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	19.436s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	14.633s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	13.495s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	12.934s		0	1	0.00
		rom_e2e_asm_init_dev	14.100s		0	1	0.00
		rom_e2e_asm_init_prod	12.449s		0	1	0.00
		rom_e2e_asm_init_prod_end	15.927s		0	1	0.00
		rom_e2e_asm_init_rma	12.796s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	11.658s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	11.558s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	11.693s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	12.520s		0	1	0.00
V2		TOTAL			65	205	31.71
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.566m	4.773ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	2.807m	2.983ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	12.491s		0	1	0.00
		rom_e2e_jtag_debug_dev	12.324s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.533s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	15.949s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	22.396m	14.037ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	11.978s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	21.824m	16.763ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	11.773s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	12.303s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	12.491s		0	1	0.00
		rom_e2e_jtag_debug_dev	12.324s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.533s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	12.407s		0	1	0.00
		rom_e2e_jtag_inject_dev	11.768s		0	1	0.00
		rom_e2e_jtag_inject_rma	12.329s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	12.678s		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	23.293m	16.408ms	1	1	100.00
		chip_sw_entropy_src_kat_test	4.654m	4.387ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	4.364m	3.707ms	1	1	100.00
		chip_plic_all_irqs_0	9.525m	5.889ms	1	1	100.00
		chip_plic_all_irqs_10	10.922m	6.953ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.307m	4.610ms	1	1	100.00
		chip_sw_dma_abort	5.010m	5.717ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	11.947s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	11.946s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	12.309s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	12.105s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	12.461s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	12.702s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	12.153s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	11.477s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	12.179s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	11.594s		0	1	0.00
		chip_sw_entropy_src_smoketest	4.869m	4.393ms	1	1	100.00
		chip_sw_mbx_smoketest	4.042m	3.908ms	1	1	100.00
		TOTAL			79	250	31.60

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.13615498832217827221356419752141707916334359076231490045118581099086140670399
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 134.729s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.18089381445596519633345534192862359678259485408550441196715273226832125037988
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 76.285s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.28408596028255935690782783967938553882878084465092002409255014685930260048954
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 54.476s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.83187201342940969475792108954015076976045008007800634204808205638571526947247
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Target //sw/device/tests:sleep_pin_retention_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 24.335s, Critical Path: 0.03s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.62116702506365512320655841964104539644311345426063059947793122912680150160461
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 8.215s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.81077020655946465165869650923891032061630928384659907696675991779461466747654
    Line 381, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.400001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.57649960573748016776778977516576863382753946712820168588899332864056866116205
    Line 392, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.96748293423548055742691196923213546901053551345249562825119556740288518804041
    Line 378, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.104996263332694862732948079775351567208861597391558714541900161264147397472626
    Line 381, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.160001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.26716639009359063366758757073777066205356523286417371937527384889200619281454
    Line 378, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 4 failures:

Test chip_sw_clkmgr_off_aes_trans has 1 failures.

0.chip_sw_clkmgr_off_aes_trans.31212368164217900282028117364648365304402732434595439134280459874881165905724
Line 390, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12026.674339 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.674339 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

0.chip_sw_clkmgr_off_hmac_trans.106241508701313739494375134556437796284685149884676282332727637413278825923008
Line 395, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12026.964540 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.964540 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_kmac_trans has 1 failures.

0.chip_sw_clkmgr_off_kmac_trans.66583096028055428197420203894115870123464146848924924090603475740427681325755
Line 391, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12026.719582 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.719582 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_otbn_trans has 1 failures.

0.chip_sw_clkmgr_off_otbn_trans.27483437637003697445579521319923474794677022527474136474251919064108432488363
Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12026.763668 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.763668 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.38336512143740107742803259280659993295681684965878089131418290105734217157107
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.25463548438128054641058123267046720279375612804203092716935518843376831939800
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.101659029706462792751403977408322042605541939396903414459019249968392124549035
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.21611541108595817498728444494593459042957183482991439305859015443404134203173
Line 426, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20018.444356 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20018.444356 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.25457547879426504184907861461800106592533517203382391572460775529271555822932
Line 401, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18018.624524 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.624524 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.14574826974075216175746287527954588080564928133359118685898864159585746415627
Line 394, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18018.580324 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.580324 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.101162368276138103288814156456335919977504465010179583929108042788090859651888
Line 405, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 8791.422248 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (10223358962181654642025637865215218346571924734353607387327169685805763127835722825409327177320318358345334053414109575986944848451446034044838806657784924 [0xc332bcd8aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd345640c297f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 8791.422248 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.3357483299133114825258463446039574701700033669157047210265438038226938864060
Line 404, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 6789.839920 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (1974323977827224503493992739007712519229634144783619269732025639144555399726062105146344920726812766929001761642008523147817083395508360824401369055452252 [0x25b24b69aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3a3e4fb987f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 6789.839920 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47301) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.46732732520605550914027011254859737279978906359737842785542552698149046205826
Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 3979.756725 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47301) { a_addr: 'h30480000  a_data: 'h610e3859  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1a  a_opcode: 'h0  a_user: 'h26941  d_param: 'h0  d_source: 'h1a  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3979.756725 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.49351560102835843781537157172022617261224307888771811350339038854647201783379
Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 2934.625655 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47301) { a_addr: 'h30480000  a_data: 'h4b3d184c  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h19  a_opcode: 'h1  a_user: 'h24895  d_param: 'h0  d_source: 'h19  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2934.625655 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.95148438967287486627013343238885930274950603539381495392526057501999742956225
    Line 1317, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.10416364351610460722544200430413601011523680618607794953530609581568939668795
    Line 416, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 5371.259180 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 5371.259180 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.11248873541343477146890842056673465507172035369755417175920708160272300711223
    Line 637, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 6554.213660 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 6554.213660 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.37219392958461791929199048242607676140677346934129288429547163964757339366377
    Line 396, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 5813.602158 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 5813.602158 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.21405259134838633167945393202792055204809463813077365186843809675372473438066
    Line 393, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 4819.546850 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 4819.546850 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.45022269282454049704988108171823511573269034474144952582436728036760535387528
    Line 388, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 3545.390340 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 3545.390340 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.72704824568920476712631134029299223684335129443828997858431140768953977825701
    Line 384, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 7048.922930 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 7048.922930 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.3642270053531625659372060922172261738236383186316381585184596022994104039461
    Line 403, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.94366453677954298998807298546291381272762299064723722531823776683190099246785
    Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 3075.770258 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 3075.770258 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.90028982377223138564520011396915413642214503021089744140444717563984461303484
    Line 375, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 14003.311840 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 14003.311840 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.87435526898621183137719211516648920242028961674414540606117031821117005506427
    Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.87851408356163096902786364369764123931866384948980986290968827180531624990260
    Line 398, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 5717.104812 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 5717.104812 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```