DMA Simulation Results

Tuesday October 21 2025 16:03:41 UTC

GitHub Revision: 7c8100d

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	4.000s	1.145ms	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	5.000s	4.248ms	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	6.000s	351.599us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	2.000s	62.550us	1	1	100.00
V1	csr_rw	dma_csr_rw	2.000s	49.310us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	12.000s	1.516ms	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	4.000s	338.895us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	2.000s	147.618us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	2.000s	49.310us	1	1	100.00
		dma_csr_aliasing	4.000s	338.895us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	47.000s	4.086ms	1	1	100.00
V2	dma_memory_tl_error	dma_memory_stress	8.567m	180.548ms	1	1	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	28.133m	299.586ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	28.133m	299.586ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	8.567m	180.548ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	6.600m	171.832ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	28.133m	299.586ms	1	1	100.00
V2	dma_abort	dma_abort	7.000s	710.869us	1	1	100.00
V2	dma_stress_all	dma_stress_all	5.150m	24.725ms	1	1	100.00
V2	alert_test	dma_alert_test	1.000s	35.959us	1	1	100.00
V2	intr_test	dma_intr_test	2.000s	16.119us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	3.000s	39.172us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	3.000s	39.172us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	2.000s	62.550us	1	1	100.00
		dma_csr_rw	2.000s	49.310us	1	1	100.00
		dma_csr_aliasing	4.000s	338.895us	1	1	100.00
		dma_same_csr_outstanding	2.000s	39.464us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	2.000s	62.550us	1	1	100.00
		dma_csr_rw	2.000s	49.310us	1	1	100.00
		dma_csr_aliasing	4.000s	338.895us	1	1	100.00
		dma_same_csr_outstanding	2.000s	39.464us	1	1	100.00
V2		TOTAL			10	10	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	20.000s	1.539ms	1	1	100.00
		dma_generic_stress	6.600m	171.832ms	1	1	100.00
		dma_handshake_stress	28.133m	299.586ms	1	1	100.00
V2S	dma_config_lock	dma_config_lock	7.000s	807.739us	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	3.000s	330.073us	1	1	100.00
		dma_sec_cm	2.000s	19.750us	1	1	100.00
V2S		TOTAL			4	4	100.00
	Unmapped tests	dma_short_transfer	1.967m	29.605ms	1	1	100.00
		dma_longer_transfer	7.000s	230.990us	1	1	100.00
		dma_stress_all_with_rand_reset	4.000s	110.934us	0	1	0.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.61557560571531905358261647927110201920089874864968436661504847999139665044339
      Line 93, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  110934186ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10004 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @  110934186ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---