EDN Simulation Results

Tuesday October 21 2025 16:03:41 UTC

GitHub Revision: 7c8100d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.940s	24.312us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.900s	20.564us	1	1	100.00
V1	csr_rw	edn_csr_rw	0.840s	21.591us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	1.830s	304.585us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.300s	32.915us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	0.950s	56.047us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.840s	21.591us	1	1	100.00
		edn_csr_aliasing	1.300s	32.915us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	2.210s	114.571us	1	1	100.00
V2	csrng_commands	edn_genbits	2.210s	114.571us	1	1	100.00
V2	genbits	edn_genbits	2.210s	114.571us	1	1	100.00
V2	interrupts	edn_intr	0.900s	23.199us	1	1	100.00
V2	alerts	edn_alert	0.980s	222.948us	1	1	100.00
V2	errs	edn_err	0.920s	30.663us	1	1	100.00
V2	disable	edn_disable	0.840s	22.625us	1	1	100.00
		edn_disable_auto_req_mode	1.010s	29.482us	1	1	100.00
V2	stress_all	edn_stress_all	2.400s	837.251us	1	1	100.00
V2	intr_test	edn_intr_test	0.860s	21.684us	1	1	100.00
V2	alert_test	edn_alert_test	0.850s	15.107us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	1.280s	89.314us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	1.280s	89.314us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.900s	20.564us	1	1	100.00
		edn_csr_rw	0.840s	21.591us	1	1	100.00
		edn_csr_aliasing	1.300s	32.915us	1	1	100.00
		edn_same_csr_outstanding	0.980s	26.110us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.900s	20.564us	1	1	100.00
		edn_csr_rw	0.840s	21.591us	1	1	100.00
		edn_csr_aliasing	1.300s	32.915us	1	1	100.00
		edn_same_csr_outstanding	0.980s	26.110us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	3.540s	496.611us	1	1	100.00
		edn_tl_intg_err	1.340s	78.512us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.860s	78.000us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	0.980s	222.948us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	3.540s	496.611us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	3.540s	496.611us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	3.540s	496.611us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	3.540s	496.611us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	0.980s	222.948us	1	1	100.00
		edn_sec_cm	3.540s	496.611us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	0.980s	222.948us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	1.340s	78.512us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	33.890s	2.436ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00