HMAC Simulation Results

Tuesday October 21 2025 16:03:41 UTC

GitHub Revision: 7c8100d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 10.030s 830.288us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 0.950s 25.526us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.900s 30.480us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 10.300s 639.048us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 3.880s 1.027ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.710s 26.852us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.900s 30.480us 1 1 100.00
hmac_csr_aliasing 3.880s 1.027ms 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 7.010s 682.936us 1 1 100.00
V2 back_pressure hmac_back_pressure 55.100s 3.959ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 7.700s 183.388us 1 1 100.00
hmac_test_sha384_vectors 18.770s 326.667us 1 1 100.00
hmac_test_sha512_vectors 6.383m 21.892ms 1 1 100.00
hmac_test_hmac256_vectors 10.170s 688.180us 1 1 100.00
hmac_test_hmac384_vectors 6.650s 811.216us 1 1 100.00
hmac_test_hmac512_vectors 9.280s 1.247ms 1 1 100.00
V2 burst_wr hmac_burst_wr 9.770s 775.092us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 1.916m 939.914us 1 1 100.00
V2 error hmac_error 51.930s 2.371ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.041m 1.540ms 1 1 100.00
V2 save_and_restore hmac_smoke 10.030s 830.288us 1 1 100.00
hmac_long_msg 7.010s 682.936us 1 1 100.00
hmac_back_pressure 55.100s 3.959ms 1 1 100.00
hmac_datapath_stress 1.916m 939.914us 1 1 100.00
hmac_burst_wr 9.770s 775.092us 1 1 100.00
hmac_stress_all 11.213m 349.849ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 10.030s 830.288us 1 1 100.00
hmac_long_msg 7.010s 682.936us 1 1 100.00
hmac_back_pressure 55.100s 3.959ms 1 1 100.00
hmac_datapath_stress 1.916m 939.914us 1 1 100.00
hmac_wipe_secret 1.041m 1.540ms 1 1 100.00
hmac_test_sha256_vectors 7.700s 183.388us 1 1 100.00
hmac_test_sha384_vectors 18.770s 326.667us 1 1 100.00
hmac_test_sha512_vectors 6.383m 21.892ms 1 1 100.00
hmac_test_hmac256_vectors 10.170s 688.180us 1 1 100.00
hmac_test_hmac384_vectors 6.650s 811.216us 1 1 100.00
hmac_test_hmac512_vectors 9.280s 1.247ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 10.030s 830.288us 1 1 100.00
hmac_long_msg 7.010s 682.936us 1 1 100.00
hmac_back_pressure 55.100s 3.959ms 1 1 100.00
hmac_datapath_stress 1.916m 939.914us 1 1 100.00
hmac_burst_wr 9.770s 775.092us 1 1 100.00
hmac_error 51.930s 2.371ms 1 1 100.00
hmac_wipe_secret 1.041m 1.540ms 1 1 100.00
hmac_test_sha256_vectors 7.700s 183.388us 1 1 100.00
hmac_test_sha384_vectors 18.770s 326.667us 1 1 100.00
hmac_test_sha512_vectors 6.383m 21.892ms 1 1 100.00
hmac_test_hmac256_vectors 10.170s 688.180us 1 1 100.00
hmac_test_hmac384_vectors 6.650s 811.216us 1 1 100.00
hmac_test_hmac512_vectors 9.280s 1.247ms 1 1 100.00
hmac_stress_all 11.213m 349.849ms 1 1 100.00
V2 stress_all hmac_stress_all 11.213m 349.849ms 1 1 100.00
V2 alert_test hmac_alert_test 0.800s 20.068us 1 1 100.00
V2 intr_test hmac_intr_test 0.890s 58.757us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.120s 48.332us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.120s 48.332us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.950s 25.526us 1 1 100.00
hmac_csr_rw 0.900s 30.480us 1 1 100.00
hmac_csr_aliasing 3.880s 1.027ms 1 1 100.00
hmac_same_csr_outstanding 1.320s 176.994us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 0.950s 25.526us 1 1 100.00
hmac_csr_rw 0.900s 30.480us 1 1 100.00
hmac_csr_aliasing 3.880s 1.027ms 1 1 100.00
hmac_same_csr_outstanding 1.320s 176.994us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.040s 113.206us 1 1 100.00
hmac_tl_intg_err 3.210s 928.432us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.210s 928.432us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 10.030s 830.288us 1 1 100.00
V3 stress_reset hmac_stress_reset 0.780s 206.154us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 56.440s 18.595ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 3.130s 1.117ms 1 1 100.00
TOTAL 28 28 100.00