I2C Simulation Results

Tuesday October 21 2025 16:03:41 UTC

GitHub Revision: `7c8100d`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.097m	7.889ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	14.170s	748.342us	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	0.680s	21.368us	1	1	100.00
V1	csr_rw	i2c_csr_rw	0.690s	24.840us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.680s	4.013ms	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.000s	63.624us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	0.890s	77.723us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	0.690s	24.840us	1	1	100.00
		i2c_csr_aliasing	1.000s	63.624us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	0.830s	35.620us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	17.767m	35.084ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	1.730m	12.248ms	1	1	100.00
V2	host_override	i2c_host_override	0.660s	16.755us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.806m	2.776ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	57.870s	11.198ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.180s	179.216us	1	1	100.00
		i2c_host_fifo_fmt_empty	3.700s	1.359ms	1	1	100.00
		i2c_host_fifo_reset_rx	7.290s	200.043us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	26.270s	18.242ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	7.340s	569.124us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	0.680s	15.785us	0	1	0.00
V2	target_glitch	i2c_target_glitch	1.800s	878.452us	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	1.523m	33.651ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	2.990s	1.346ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	11.900s	2.344ms	1	1	100.00
		i2c_target_intr_smoke	3.220s	957.151us	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.290s	267.276us	1	1	100.00
		i2c_target_fifo_reset_tx	0.910s	173.923us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	42.360s	30.263ms	1	1	100.00
		i2c_target_stress_rd	11.900s	2.344ms	1	1	100.00
		i2c_target_intr_stress_wr	3.361m	17.588ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	4.890s	20.585ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	17.140s	4.298ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.800s	1.084ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	4.250s	10.077ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	1.820s	3.799ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.250s	594.397us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	1.730m	12.248ms	1	1	100.00
		i2c_host_perf_precise	2.200s	256.231us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	7.340s	569.124us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.410s	193.820us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	1.810s	941.680us	1	1	100.00
		i2c_target_nack_acqfull_addr	1.970s	512.937us	1	1	100.00
		i2c_target_nack_txstretch	1.100s	282.600us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	2.690s	1.214ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.780s	1.169ms	1	1	100.00
V2	alert_test	i2c_alert_test	0.610s	27.723us	1	1	100.00
V2	intr_test	i2c_intr_test	0.720s	21.845us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.620s	189.622us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.620s	189.622us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	0.680s	21.368us	1	1	100.00
		i2c_csr_rw	0.690s	24.840us	1	1	100.00
		i2c_csr_aliasing	1.000s	63.624us	1	1	100.00
		i2c_same_csr_outstanding	0.760s	110.893us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	0.680s	21.368us	1	1	100.00
		i2c_csr_rw	0.690s	24.840us	1	1	100.00
		i2c_csr_aliasing	1.000s	63.624us	1	1	100.00
		i2c_same_csr_outstanding	0.760s	110.893us	1	1	100.00
V2		TOTAL			33	38	86.84
V2S	tl_intg_err	i2c_tl_intg_err	1.740s	245.695us	1	1	100.00
		i2c_sec_cm	0.810s	54.760us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	1.740s	245.695us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	8.950s	1.382ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.130s	708.951us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	7.130s	783.791us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			42	50	84.00

Failure Buckets

UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 4 failures:

Test i2c_host_error_intr has 1 failures.

0.i2c_host_error_intr.74195987878637950247747189774723764219826083083056438618995008642732322437029
Line 96, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

  UVM_ERROR @  35619751 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  35619751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.95860017347978771513197498768268132864509604023575647492015245855510612022475
Line 174, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 35084365420 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 35084365420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test i2c_target_stress_all_with_rand_reset has 1 failures.
- 0.i2c_target_stress_all_with_rand_reset.84786173617453989826316723932298860293000547614698676469238672958872541914480
  Line 93, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 783791368 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @ 783791368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Test i2c_host_mode_toggle has 1 failures.

0.i2c_host_mode_toggle.50399785608636725024439704662028361091006570081912690595289111197992911843004
Line 83, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  15784659 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
  UVM_INFO @  15784659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:
- Test i2c_target_glitch has 1 failures.
  - 0.i2c_target_glitch.39322363467548107145254838130491027720415129907557201964698256512362211269383
    Line 86, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log
```
  UVM_ERROR @ 878452377 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
  UVM_INFO @ 878452377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.1101579615885589638357590687555116577402830813801548266732672123707749195170
    Line 80, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 708950997 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 130 [0x82])
  UVM_INFO @ 708950997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:
- Test i2c_target_hrst has 1 failures.
  - 0.i2c_target_hrst.64595772497446154754538211931865443674058124425557887827609421216312715221084
    Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10077278020 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10077278020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.92412103927006776352628988274837213219912550427857654601252729440217950546803
    Line 108, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1381502576 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1381502576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```