KEYMGR Simulation Results

Tuesday October 21 2025 16:03:41 UTC

GitHub Revision: 7c8100d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 1.820s 72.626us 1 1 100.00
V1 random keymgr_random 6.080s 329.534us 1 1 100.00
V1 csr_hw_reset keymgr_csr_hw_reset 0.790s 13.105us 1 1 100.00
V1 csr_rw keymgr_csr_rw 0.860s 13.196us 1 1 100.00
V1 csr_bit_bash keymgr_csr_bit_bash 11.170s 1.268ms 1 1 100.00
V1 csr_aliasing keymgr_csr_aliasing 8.780s 1.589ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 1.090s 91.354us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 0.860s 13.196us 1 1 100.00
keymgr_csr_aliasing 8.780s 1.589ms 1 1 100.00
V1 TOTAL 7 7 100.00
V2 cfgen_during_op keymgr_cfg_regwen 2.770s 225.976us 1 1 100.00
V2 sideload keymgr_sideload 2.450s 69.386us 1 1 100.00
keymgr_sideload_kmac 8.520s 493.469us 1 1 100.00
keymgr_sideload_aes 1.890s 135.888us 1 1 100.00
keymgr_sideload_otbn 2.480s 382.254us 1 1 100.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 1.500s 35.652us 1 1 100.00
V2 lc_disable keymgr_lc_disable 2.710s 115.707us 1 1 100.00
V2 kmac_error_response keymgr_kmac_rsp_err 1.730s 451.345us 1 1 100.00
V2 invalid_sw_input keymgr_sw_invalid_input 2.350s 101.323us 1 1 100.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 2.950s 181.180us 1 1 100.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 1.480s 58.409us 1 1 100.00
V2 stress_all keymgr_stress_all 2.159m 32.040ms 1 1 100.00
V2 intr_test keymgr_intr_test 0.720s 30.277us 1 1 100.00
V2 alert_test keymgr_alert_test 0.880s 21.524us 1 1 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 1.300s 45.135us 1 1 100.00
V2 tl_d_illegal_access keymgr_tl_errors 1.300s 45.135us 1 1 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 0.790s 13.105us 1 1 100.00
keymgr_csr_rw 0.860s 13.196us 1 1 100.00
keymgr_csr_aliasing 8.780s 1.589ms 1 1 100.00
keymgr_same_csr_outstanding 1.290s 62.534us 1 1 100.00
V2 tl_d_partial_access keymgr_csr_hw_reset 0.790s 13.105us 1 1 100.00
keymgr_csr_rw 0.860s 13.196us 1 1 100.00
keymgr_csr_aliasing 8.780s 1.589ms 1 1 100.00
keymgr_same_csr_outstanding 1.290s 62.534us 1 1 100.00
V2 TOTAL 16 16 100.00
V2S sec_cm_additional_check keymgr_sec_cm 8.420s 2.347ms 1 1 100.00
V2S tl_intg_err keymgr_sec_cm 8.420s 2.347ms 1 1 100.00
keymgr_tl_intg_err 2.470s 600.478us 1 1 100.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 1.760s 471.022us 1 1 100.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 1.760s 471.022us 1 1 100.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 1.760s 471.022us 1 1 100.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 1.760s 471.022us 1 1 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 5.270s 398.911us 1 1 100.00
V2S prim_count_check keymgr_sec_cm 8.420s 2.347ms 1 1 100.00
V2S prim_fsm_check keymgr_sec_cm 8.420s 2.347ms 1 1 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 2.470s 600.478us 1 1 100.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 1.760s 471.022us 1 1 100.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 2.770s 225.976us 1 1 100.00
V2S sec_cm_reseed_config_regwen keymgr_random 6.080s 329.534us 1 1 100.00
keymgr_csr_rw 0.860s 13.196us 1 1 100.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 6.080s 329.534us 1 1 100.00
keymgr_csr_rw 0.860s 13.196us 1 1 100.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 6.080s 329.534us 1 1 100.00
keymgr_csr_rw 0.860s 13.196us 1 1 100.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 2.710s 115.707us 1 1 100.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 2.950s 181.180us 1 1 100.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 2.950s 181.180us 1 1 100.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 6.080s 329.534us 1 1 100.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 3.090s 489.215us 1 1 100.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 8.420s 2.347ms 1 1 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 8.420s 2.347ms 1 1 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 8.420s 2.347ms 1 1 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 2.730s 184.931us 1 1 100.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 2.710s 115.707us 1 1 100.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 8.420s 2.347ms 1 1 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 8.420s 2.347ms 1 1 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 8.420s 2.347ms 1 1 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 2.730s 184.931us 1 1 100.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 2.730s 184.931us 1 1 100.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 8.420s 2.347ms 1 1 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 2.730s 184.931us 1 1 100.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 8.420s 2.347ms 1 1 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 2.730s 184.931us 1 1 100.00
V2S TOTAL 6 6 100.00
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 11.200s 456.854us 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 30 30 100.00