| V1 |
smoke |
keymgr_dpe_smoke |
29.880s |
2.752ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
keymgr_dpe_csr_hw_reset |
1.040s |
50.226us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
keymgr_dpe_csr_rw |
0.940s |
39.031us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
keymgr_dpe_csr_bit_bash |
3.550s |
91.376us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
keymgr_dpe_csr_aliasing |
2.900s |
510.358us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
keymgr_dpe_csr_mem_rw_with_rand_reset |
1.180s |
88.305us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
keymgr_dpe_csr_rw |
0.940s |
39.031us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
2.900s |
510.358us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
intr_test |
keymgr_dpe_intr_test |
0.800s |
12.591us |
1 |
1 |
100.00 |
| V2 |
alert_test |
keymgr_dpe_alert_test |
0.640s |
34.737us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
keymgr_dpe_tl_errors |
2.140s |
128.602us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
keymgr_dpe_tl_errors |
2.140s |
128.602us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
keymgr_dpe_csr_hw_reset |
1.040s |
50.226us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
0.940s |
39.031us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
2.900s |
510.358us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
3.450s |
191.534us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
keymgr_dpe_csr_hw_reset |
1.040s |
50.226us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
0.940s |
39.031us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
2.900s |
510.358us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
3.450s |
191.534us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
4 |
4 |
100.00 |
| V2S |
tl_intg_err |
keymgr_dpe_sec_cm |
13.670s |
1.310ms |
1 |
1 |
100.00 |
|
|
keymgr_dpe_tl_intg_err |
3.220s |
409.878us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error |
keymgr_dpe_shadow_reg_errors |
2.410s |
282.652us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
keymgr_dpe_shadow_reg_errors |
2.410s |
282.652us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
keymgr_dpe_shadow_reg_errors |
2.410s |
282.652us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
keymgr_dpe_shadow_reg_errors |
2.410s |
282.652us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
keymgr_dpe_shadow_reg_errors_with_csr_rw |
1.990s |
55.196us |
1 |
1 |
100.00 |
| V2S |
prim_count_check |
keymgr_dpe_sec_cm |
13.670s |
1.310ms |
1 |
1 |
100.00 |
| V2S |
prim_fsm_check |
keymgr_dpe_sec_cm |
13.670s |
1.310ms |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
4 |
4 |
100.00 |
|
|
TOTAL |
|
|
14 |
14 |
100.00 |