7c8100d| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 28.000s | 9.421ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 2.000s | 61.052us | 1 | 1 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 1.000s | 20.592us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 3.000s | 656.709us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 2.000s | 38.546us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 2.000s | 154.126us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 1.000s | 20.592us | 1 | 1 | 100.00 |
| mbx_csr_aliasing | 2.000s | 38.546us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 6 | 6 | 100.00 | |||
| V2 | mbx_stress | mbx_stress | 6.000s | 1.073ms | 0 | 1 | 0.00 |
| V2 | mbx_max_activity | mbx_stress_zero_delays | 2.483m | 28.055ms | 1 | 1 | 100.00 |
| V2 | mbx_imbx_oob | mbx_imbx_oob | 17.000s | 1.713ms | 1 | 1 | 100.00 |
| V2 | mbx_doe_intr_msg | mbx_doe_intr_msg | 19.000s | 1.618ms | 1 | 1 | 100.00 |
| V2 | alert_test | mbx_alert_test | 2.000s | 38.253us | 1 | 1 | 100.00 |
| V2 | intr_test | mbx_intr_test | 1.000s | 22.342us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 3.000s | 577.991us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 3.000s | 577.991us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 2.000s | 61.052us | 1 | 1 | 100.00 |
| mbx_csr_rw | 1.000s | 20.592us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 2.000s | 38.546us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 1.000s | 38.849us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 2.000s | 61.052us | 1 | 1 | 100.00 |
| mbx_csr_rw | 1.000s | 20.592us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 2.000s | 38.546us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 1.000s | 38.849us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 7 | 8 | 87.50 | |||
| V2S | tl_intg_err | mbx_tl_intg_err | 1.000s | 104.601us | 1 | 1 | 100.00 |
| mbx_sec_cm | 1.000s | 21.137us | 1 | 1 | 100.00 | ||
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| TOTAL | 15 | 16 | 93.75 |
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register has 1 failures:
0.mbx_stress.80320002651729436095949661743165212657652750789368111330180420658535166960669
Line 554, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress/latest/run.log
UVM_ERROR @ 1073335220 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 1073335220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---