ROM_CTRL/32KB Simulation Results

Tuesday October 21 2025 16:03:41 UTC

GitHub Revision: 7c8100d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	4.040s	1.044ms	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	5.100s	545.615us	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	4.580s	174.591us	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	3.600s	415.859us	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	3.090s	387.307us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	4.100s	601.010us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	4.580s	174.591us	1	1	100.00
		rom_ctrl_csr_aliasing	3.090s	387.307us	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	4.300s	130.207us	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	3.300s	206.865us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	5.250s	187.820us	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	12.300s	1.691ms	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	8.900s	1.430ms	1	1	100.00
V2	alert_test	rom_ctrl_alert_test	3.600s	601.560us	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	7.270s	180.905us	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	7.270s	180.905us	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	5.100s	545.615us	1	1	100.00
		rom_ctrl_csr_rw	4.580s	174.591us	1	1	100.00
		rom_ctrl_csr_aliasing	3.090s	387.307us	1	1	100.00
		rom_ctrl_same_csr_outstanding	3.580s	205.930us	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	5.100s	545.615us	1	1	100.00
		rom_ctrl_csr_rw	4.580s	174.591us	1	1	100.00
		rom_ctrl_csr_aliasing	3.090s	387.307us	1	1	100.00
		rom_ctrl_same_csr_outstanding	3.580s	205.930us	1	1	100.00
V2		TOTAL			6	6	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	35.200s	1.382ms	1	1	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	18.130s	578.376us	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.798m	3.338ms	0	1	0.00
		rom_ctrl_tl_intg_err	24.100s	239.451us	1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.798m	3.338ms	0	1	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	3.798m	3.338ms	0	1	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	35.200s	1.382ms	1	1	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	35.200s	1.382ms	1	1	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	35.200s	1.382ms	1	1	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	35.200s	1.382ms	1	1	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	35.200s	1.382ms	1	1	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.798m	3.338ms	0	1	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.798m	3.338ms	0	1	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	4.040s	1.044ms	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	4.040s	1.044ms	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	4.040s	1.044ms	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	24.100s	239.451us	1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	35.200s	1.382ms	1	1	100.00
		rom_ctrl_kmac_err_chk	8.900s	1.430ms	1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	35.200s	1.382ms	1	1	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	35.200s	1.382ms	1	1	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	35.200s	1.382ms	1	1	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	18.130s	578.376us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.798m	3.338ms	0	1	0.00
V2S		TOTAL			3	4	75.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	1.036m	2.508ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			18	19	94.74

Failure Buckets

• Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))' has 1 failures:
  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.80953589258512167275647245406613103334953656193928434029486394125460131549703
      Line 240, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_opcode === (((curr_fwd ? curr_req.opcode : pend_req[d2h.d_source].opcode) == Get) ? AccessAckData : AccessAck))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 120015316ps failed at 120015316ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 120015316ps failed at 120015316ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'