7c8100d| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | random | rv_timer_random | 0.960s | 793.973us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | rv_timer_csr_hw_reset | 0.620s | 59.758us | 1 | 1 | 100.00 |
| V1 | csr_rw | rv_timer_csr_rw | 0.550s | 31.227us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | rv_timer_csr_bit_bash | 2.490s | 290.782us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | rv_timer_csr_aliasing | 0.760s | 48.802us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_timer_csr_mem_rw_with_rand_reset | 0.850s | 21.323us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_timer_csr_rw | 0.550s | 31.227us | 1 | 1 | 100.00 |
| rv_timer_csr_aliasing | 0.760s | 48.802us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 6 | 6 | 100.00 | |||
| V2 | random_reset | rv_timer_random_reset | 0.640s | 186.204us | 0 | 1 | 0.00 |
| V2 | disabled | rv_timer_disabled | 0.600s | 63.186us | 1 | 1 | 100.00 |
| V2 | cfg_update_on_fly | rv_timer_cfg_update_on_fly | 45.440s | 270.729ms | 1 | 1 | 100.00 |
| V2 | no_interrupt_test | rv_timer_cfg_update_on_fly | 45.440s | 270.729ms | 1 | 1 | 100.00 |
| V2 | stress | rv_timer_stress_all | 1.560s | 297.666us | 1 | 1 | 100.00 |
| V2 | alert_test | rv_timer_alert_test | 0.530s | 12.424us | 1 | 1 | 100.00 |
| V2 | intr_test | rv_timer_intr_test | 0.570s | 63.546us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_timer_tl_errors | 1.200s | 25.057us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | rv_timer_tl_errors | 1.200s | 25.057us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | rv_timer_csr_hw_reset | 0.620s | 59.758us | 1 | 1 | 100.00 |
| rv_timer_csr_rw | 0.550s | 31.227us | 1 | 1 | 100.00 | ||
| rv_timer_csr_aliasing | 0.760s | 48.802us | 1 | 1 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.810s | 74.853us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | rv_timer_csr_hw_reset | 0.620s | 59.758us | 1 | 1 | 100.00 |
| rv_timer_csr_rw | 0.550s | 31.227us | 1 | 1 | 100.00 | ||
| rv_timer_csr_aliasing | 0.760s | 48.802us | 1 | 1 | 100.00 | ||
| rv_timer_same_csr_outstanding | 0.810s | 74.853us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 7 | 8 | 87.50 | |||
| V2S | tl_intg_err | rv_timer_sec_cm | 0.840s | 279.477us | 1 | 1 | 100.00 |
| rv_timer_tl_intg_err | 1.170s | 248.864us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | rv_timer_tl_intg_err | 1.170s | 248.864us | 1 | 1 | 100.00 |
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| V3 | min_value | rv_timer_min | 0.660s | 233.555us | 0 | 1 | 0.00 |
| V3 | max_value | rv_timer_max | 0.580s | 173.794us | 0 | 1 | 0.00 |
| V3 | stress_all_with_rand_reset | rv_timer_stress_all_with_rand_reset | 12.920s | 2.332ms | 1 | 1 | 100.00 |
| V3 | TOTAL | 1 | 3 | 33.33 | |||
| TOTAL | 16 | 19 | 84.21 |
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 2 failures:
Test rv_timer_min has 1 failures.
0.rv_timer_min.23029281365353496121564970728661476795265455349990005405882497143518705537094
Line 77, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log
UVM_FATAL @ 233555226 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xb62ab04) == 0x1
UVM_INFO @ 233555226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_timer_random_reset has 1 failures.
0.rv_timer_random_reset.79901732072574706604552277616725828007256245293794995278360539965642069829612
Line 77, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log
UVM_FATAL @ 186204433 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x893e2304) == 0x1
UVM_INFO @ 186204433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:
0.rv_timer_max.55923191264965339049970343629591745318768917459519366155937797663019901577468
Line 77, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log
UVM_ERROR @ 173793992 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 173793992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---