SPI_DEVICE/1R1W Simulation Results

Tuesday October 21 2025 16:03:41 UTC

GitHub Revision: 7c8100d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	53.780s	12.111ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.070s	46.763us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.930s	421.762us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	25.570s	2.847ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	5.610s	754.304us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.430s	278.664us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.930s	421.762us	1	1	100.00
		spi_device_csr_aliasing	5.610s	754.304us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.620s	35.660us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.400s	78.081us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	0.750s	133.046us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	0.690s	3.193us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.650s	5.200us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	0.930s	36.877us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	0.930s	36.877us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	4.060s	1.527ms	1	1	100.00
		spi_device_tpm_sts_read	0.730s	30.672us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	12.010s	45.432ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	5.170s	3.979ms	1	1	100.00
		spi_device_flash_all	37.330s	4.723ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	2.150s	1.649ms	1	1	100.00
		spi_device_flash_all	37.330s	4.723ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	2.150s	1.649ms	1	1	100.00
		spi_device_flash_all	37.330s	4.723ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	37.330s	4.723ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	7.620s	2.907ms	1	1	100.00
		spi_device_flash_all	37.330s	4.723ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	7.620s	2.907ms	1	1	100.00
		spi_device_flash_all	37.330s	4.723ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	7.620s	2.907ms	1	1	100.00
		spi_device_flash_all	37.330s	4.723ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	7.620s	2.907ms	1	1	100.00
		spi_device_flash_all	37.330s	4.723ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	7.620s	2.907ms	1	1	100.00
		spi_device_flash_all	37.330s	4.723ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	4.440s	1.520ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	32.840s	6.332ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	32.840s	6.332ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	32.840s	6.332ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	3.460s	186.673us	1	1	100.00
		spi_device_read_buffer_direct	2.310s	951.940us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	32.840s	6.332ms	1	1	100.00
		spi_device_flash_all	37.330s	4.723ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	37.330s	4.723ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	37.330s	4.723ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.540s	172.035us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.540s	172.035us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	53.780s	12.111ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.156m	11.713ms	1	1	100.00
V2	stress_all	spi_device_stress_all	0.960s	336.144us	1	1	100.00
V2	alert_test	spi_device_alert_test	0.710s	52.545us	1	1	100.00
V2	intr_test	spi_device_intr_test	0.660s	47.650us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.960s	318.058us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.960s	318.058us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.070s	46.763us	1	1	100.00
		spi_device_csr_rw	1.930s	421.762us	1	1	100.00
		spi_device_csr_aliasing	5.610s	754.304us	1	1	100.00
		spi_device_same_csr_outstanding	2.090s	160.609us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.070s	46.763us	1	1	100.00
		spi_device_csr_rw	1.930s	421.762us	1	1	100.00
		spi_device_csr_aliasing	5.610s	754.304us	1	1	100.00
		spi_device_same_csr_outstanding	2.090s	160.609us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	0.980s	255.656us	1	1	100.00
		spi_device_tl_intg_err	12.450s	581.191us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	12.450s	581.191us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	0.660s	168.116us	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.58138736790605269001653545612270074457929694372880289273508044977306054216339
      Line 78, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   2213095 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[16])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   2213095 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   2213095 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[912])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.5970271855748854297847002955451584834207730751017963100745822086572674020552
      Line 78, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   2752785 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xbcb660 [101111001011011001100000] vs 0x0 [0])
        UVM_ERROR @   2827785 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x81d412 [100000011101010000010010] vs 0x0 [0])
        UVM_ERROR @   2876785 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xcc8cb0 [110011001000110010110000] vs 0x0 [0])
        UVM_ERROR @   2962785 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa0fab5 [101000001111101010110101] vs 0x0 [0])
        UVM_ERROR @   2963785 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x80afcd [100000001010111111001101] vs 0x0 [0])