SPI_HOST Simulation Results

Tuesday October 21 2025 16:03:41 UTC

GitHub Revision: 7c8100d

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	13.000s	1.062ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	1.000s	29.923us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	1.000s	34.263us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	2.000s	163.228us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	61.329us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	88.631us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	1.000s	34.263us	1	1	100.00
		spi_host_csr_aliasing	2.000s	61.329us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	1.000s	40.905us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	1.000s	67.380us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	6.000s	56.248us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	5.000s	27.254us	1	1	100.00
		spi_host_error_cmd	5.000s	19.068us	1	1	100.00
		spi_host_event	5.000s	191.191us	1	1	100.00
V2	clock_rate	spi_host_speed	8.000s	93.432us	1	1	100.00
V2	speed	spi_host_speed	8.000s	93.432us	1	1	100.00
V2	chip_select_timing	spi_host_speed	8.000s	93.432us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	8.000s	128.693us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	29.158us	1	1	100.00
V2	cpol_cpha	spi_host_speed	8.000s	93.432us	1	1	100.00
V2	full_cycle	spi_host_speed	8.000s	93.432us	1	1	100.00
V2	duplex	spi_host_smoke	13.000s	1.062ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	13.000s	1.062ms	1	1	100.00
V2	stress_all	spi_host_stress_all	3.000s	105.612us	1	1	100.00
V2	spien	spi_host_spien	2.000s	132.461us	1	1	100.00
V2	stall	spi_host_status_stall	58.000s	25.392ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	3.000s	324.838us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	5.000s	27.254us	1	1	100.00
V2	alert_test	spi_host_alert_test	1.000s	52.084us	1	1	100.00
V2	intr_test	spi_host_intr_test	1.000s	38.010us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	2.000s	1.206ms	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	2.000s	1.206ms	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	1.000s	29.923us	1	1	100.00
		spi_host_csr_rw	1.000s	34.263us	1	1	100.00
		spi_host_csr_aliasing	2.000s	61.329us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	68.315us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	1.000s	29.923us	1	1	100.00
		spi_host_csr_rw	1.000s	34.263us	1	1	100.00
		spi_host_csr_aliasing	2.000s	61.329us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	68.315us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	1.000s	87.853us	1	1	100.00
		spi_host_sec_cm	1.000s	60.061us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	1.000s	87.853us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	42.000s	5.451ms	1	1	100.00
		TOTAL			26	26	100.00