SRAM_CTRL/MAIN Simulation Results

Tuesday October 21 2025 16:03:41 UTC

GitHub Revision: 7c8100d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	11.190s	2.450ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.940s	60.341us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.820s	29.228us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.530s	115.982us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.000s	43.631us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.690s	868.442us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.820s	29.228us	1	1	100.00
		sram_ctrl_csr_aliasing	1.000s	43.631us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	4.044m	82.697ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.690m	4.945ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	8.226m	62.358ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.235m	4.795ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	14.771m	173.764ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	17.741m	41.684ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	39.750s	152.102ms	1	1	100.00
V2	executable	sram_ctrl_executable	13.772m	33.689ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	11.990s	2.062ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.638m	24.159ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	45.020s	1.620ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	47.010s	3.333ms	1	1	100.00
		sram_ctrl_throughput_w_readback	1.070m	918.938us	1	1	100.00
V2	regwen	sram_ctrl_regwen	4.835m	1.643ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.410s	1.398ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	31.314m	42.209ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	0.660s	16.035us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.100s	516.088us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.100s	516.088us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.940s	60.341us	1	1	100.00
		sram_ctrl_csr_rw	0.820s	29.228us	1	1	100.00
		sram_ctrl_csr_aliasing	1.000s	43.631us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.920s	27.979us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.940s	60.341us	1	1	100.00
		sram_ctrl_csr_rw	0.820s	29.228us	1	1	100.00
		sram_ctrl_csr_aliasing	1.000s	43.631us	1	1	100.00
		sram_ctrl_same_csr_outstanding	0.920s	27.979us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	46.340s	64.093ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	0.790s	8.862us	0	1	0.00
		sram_ctrl_tl_intg_err	1.790s	339.267us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	0.790s	8.862us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	1.790s	339.267us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	4.835m	1.643ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	4.835m	1.643ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.820s	29.228us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	13.772m	33.689ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	13.772m	33.689ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	13.772m	33.689ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	39.750s	152.102ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	3.840s	1.364ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	46.340s	64.093ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	3.580s	716.968us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	11.190s	2.450ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	11.190s	2.450ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	13.772m	33.689ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	0.790s	8.862us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	39.750s	152.102ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	0.790s	8.862us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	0.790s	8.862us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	11.190s	2.450ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	0.790s	8.862us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	19.720s	3.554ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.19125361360571904361500137844927166053347638645619580611445856718711999457967
      Line 104, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   8862302 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   8862302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---