UART Simulation Results

Tuesday October 21 2025 16:03:41 UTC

GitHub Revision: 7c8100d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.390s	664.521us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.690s	45.236us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.820s	59.673us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.910s	1.556ms	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.920s	31.165us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.060s	26.225us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.820s	59.673us	1	1	100.00
		uart_csr_aliasing	0.920s	31.165us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	22.080s	38.682ms	1	1	100.00
V2	parity	uart_smoke	2.390s	664.521us	1	1	100.00
		uart_tx_rx	22.080s	38.682ms	1	1	100.00
V2	parity_error	uart_intr	13.360s	12.104ms	1	1	100.00
		uart_rx_parity_err	36.810s	131.211ms	1	1	100.00
V2	watermark	uart_tx_rx	22.080s	38.682ms	1	1	100.00
		uart_intr	13.360s	12.104ms	1	1	100.00
V2	fifo_full	uart_fifo_full	43.240s	175.876ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	9.890s	19.507ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	3.339m	147.780ms	1	1	100.00
V2	rx_frame_err	uart_intr	13.360s	12.104ms	1	1	100.00
V2	rx_break_err	uart_intr	13.360s	12.104ms	1	1	100.00
V2	rx_timeout	uart_intr	13.360s	12.104ms	1	1	100.00
V2	perf	uart_perf	7.952m	14.273ms	1	1	100.00
V2	sys_loopback	uart_loopback	0.890s	1.107ms	1	1	100.00
V2	line_loopback	uart_loopback	0.890s	1.107ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	3.630s	2.362ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	3.040s	5.026ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	6.970s	9.691ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	5.930s	1.979ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	1.323m	84.318ms	1	1	100.00
V2	stress_all	uart_stress_all	11.843m	306.024ms	1	1	100.00
V2	alert_test	uart_alert_test	0.800s	27.418us	1	1	100.00
V2	intr_test	uart_intr_test	0.860s	12.024us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.350s	296.743us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.350s	296.743us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.690s	45.236us	1	1	100.00
		uart_csr_rw	0.820s	59.673us	1	1	100.00
		uart_csr_aliasing	0.920s	31.165us	1	1	100.00
		uart_same_csr_outstanding	0.910s	111.907us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.690s	45.236us	1	1	100.00
		uart_csr_rw	0.820s	59.673us	1	1	100.00
		uart_csr_aliasing	0.920s	31.165us	1	1	100.00
		uart_same_csr_outstanding	0.910s	111.907us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	1.110s	39.607us	1	1	100.00
		uart_tl_intg_err	1.350s	283.918us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.350s	283.918us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	18.310s	1.890ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.84410571610056668465045048684478297445841493675950180915843810207242679749969
      Line 72, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 2268287637 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 2268287637 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 2296447637 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 3, rx_q.size = 0
        UVM_ERROR @ 2307807637 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 2308267637 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0