CHIP Simulation Results

Tuesday October 21 2025 16:03:41 UTC

GitHub Revision: `7c8100d`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	1.514m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	1.514m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	30.234s		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.221m		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	26.799s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	7.488m	5.111ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	7.488m	5.111ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	7.488m	5.111ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	30.070s	10.300us	0	1	0.00
		chip_sw_example_manufacturer	2.237m		0	1	0.00
		chip_sw_example_concurrency	5.155m	5.056ms	1	1	100.00
		chip_sw_uart_smoketest_signed	11.390s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	11.530s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	12.140s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	12.140s		0	1	0.00
V1	xbar_smoke	xbar_smoke	9.390s	13.322us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.185m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	8.987m	7.700ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.527m	3.493ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	14.503s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	26.888s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	27.450s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	16.858s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.150s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.150s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	1.636m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	1.584m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	1.672m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	1.672m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.950m	3.807ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	2.894m	3.620ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	6.366m	14.204ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.592s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	12.332s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	6.641m	7.825ms	0	1	0.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	6.405m	5.139ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	21.098m	18.027ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	21.098m	18.027ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	16.088s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.687m	5.417ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.687m	5.417ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	5.491m	18.027ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.410m	4.459ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	6.840m	6.594ms	1	1	100.00
		chip_sw_aes_idle	4.746m	4.628ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.562m	4.809ms	1	1	100.00
		chip_sw_kmac_idle	3.638m	5.156ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	12.816m	12.027ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	14.065m	12.019ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	12.447m	12.027ms	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	12.652m	12.027ms	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	12.859s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.120s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.789s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.349s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.077s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.724s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.820s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	12.859s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.120s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.789s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.349s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.077s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.724s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.820s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	12.143s		0	1	0.00
		chip_sw_aes_enc_jitter_en	36.790s	10.160us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	36.290s	10.220us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	40.300s	10.280us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	49.700s	10.220us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.607s		0	1	0.00
		chip_sw_clkmgr_jitter	3.511m	3.773ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.097m	5.220ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	14.776s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	39.280s	10.240us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	37.960s	10.340us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	47.240s	10.300us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	36.440s	10.280us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	41.980s	10.300us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	11.953s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	12.876s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	14.651s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	12.976s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	21.720m	11.954ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	11.007m	12.771ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	4.687m	5.417ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	11.334s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	11.007m	12.771ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	21.794s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	12.427s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	15.562s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	13.403s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	13.271s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	21.720m	11.954ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	6.366m	14.204ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	24.897m	20.018ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	6.028m	7.491ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	11.810m	10.048ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.955m	3.892ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	21.720m	11.954ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	11.976s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	12.084s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	21.720m	11.954ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	12.799s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	11.810m	10.048ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	13.399s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	11.825s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	11.941s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	11.685s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	14.341s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	12.973s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	12.084s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	15.409s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	21.975s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	15.409s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	15.409s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	15.409s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	5.717m	7.532ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	17.485s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	16.636s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	31.390s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	19.120s		0	1	0.00
		chip_sw_lc_ctrl_transition	15.409s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	8.479m	9.531ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	10.459m	11.460ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	12.844s		0	1	0.00
		chip_prim_tl_access	16.006m	18.813ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	12.859s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.120s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	12.789s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.349s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.077s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.724s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.820s		0	1	0.00
		chip_rv_dm_lc_disabled	6.641m	7.825ms	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	5.916m	5.551ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	36.790s	10.160us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.787m	4.716ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.746m	4.628ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	5.269m	4.516ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	36.290s	10.220us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.562m	4.809ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.725m	4.384ms	1	1	100.00
		chip_sw_kmac_mode_kmac	4.627m	4.466ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	49.700s	10.220us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	8.479m	9.531ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	15.409s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	39.540s	10.240us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.891m	4.799ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.638m	5.156ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	13.684s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	13.684s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	14.388s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.760m	4.099ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	13.705s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	8.479m	9.531ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	40.300s	10.280us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	14.949s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	12.143s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	6.840m	6.594ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	6.840m	6.594ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	6.840m	6.594ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	8.707m	4.801ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	10.459m	11.460ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	10.459m	11.460ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	9.245m	7.760ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.607s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	12.844s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	21.720m	11.954ms	1	1	100.00
		chip_sw_data_integrity_escalation	1.672m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	15.409s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	8.707m	4.801ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	8.479m	9.531ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	9.245m	7.760ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.657m	4.576ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	8.707m	4.801ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	8.479m	9.531ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	9.245m	7.760ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.657m	4.576ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	15.409s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	11.852s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	21.975s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	17.485s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	16.636s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	31.390s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	19.120s		0	1	0.00
		chip_sw_lc_ctrl_transition	15.409s		0	1	0.00
		chip_prim_tl_access	16.006m	18.813ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	16.006m	18.813ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	13.427s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	40.381s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	12.876s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	12.143s		0	1	0.00
		chip_sw_aes_enc_jitter_en	36.790s	10.160us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	36.290s	10.220us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	40.300s	10.280us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	49.700s	10.220us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.607s		0	1	0.00
		chip_sw_clkmgr_jitter	3.511m	3.773ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	7.680m	10.228ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	7.680m	10.228ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	4.083m	3.711ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	4.209m	5.455ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	4.695m	4.527ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.202m	5.836ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	6.504m	6.206ms	0	1	0.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	5.063m	4.928ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	3.657m	4.576ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	24.897m	20.018ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	24.897m	20.018ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.775m	3.776ms	1	1	100.00
		chip_sw_aon_timer_smoketest	4.138m	4.994ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.455m	3.705ms	1	1	100.00
		chip_sw_csrng_smoketest	3.694m	3.704ms	1	1	100.00
		chip_sw_gpio_smoketest	3.612m	4.945ms	1	1	100.00
		chip_sw_hmac_smoketest	3.897m	3.795ms	1	1	100.00
		chip_sw_kmac_smoketest	4.029m	3.549ms	1	1	100.00
		chip_sw_otbn_smoketest	4.147m	4.261ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.583m	3.440ms	1	1	100.00
		chip_sw_rv_plic_smoketest	4.268m	5.176ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.464m	4.702ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.392m	3.764ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.231m	4.451ms	1	1	100.00
		chip_sw_uart_smoketest	4.204m	5.056ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	12.219s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	11.390s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.185m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	13.690s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.767m	5.186ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	4.067m	6.138ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	4.098m	3.766ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.351m	5.530ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	11.570s		0	1	0.00
		chip_rv_dm_lc_disabled	6.641m	7.825ms	0	1	0.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	12.373s		0	1	0.00
		chip_sw_lc_walkthrough_prod	15.255s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	20.705s		0	1	0.00
		chip_sw_lc_walkthrough_rma	17.081s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	11.570s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	14.830s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	12.400s		0	1	0.00
		rom_volatile_raw_unlock	11.341s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	11.382s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	42.062s		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	43.871s		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	3.437m	4.322ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	3.437m	4.322ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	12.140s		0	1	0.00
		chip_same_csr_outstanding	9.160s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	12.140s		0	1	0.00
		chip_same_csr_outstanding	9.160s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	1.888m	272.168us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	9.570s	11.942us	1	1	100.00
		xbar_smoke_large_delays	4.692m	2.464ms	1	1	100.00
		xbar_smoke_slow_rsp	6.098m	2.245ms	1	1	100.00
		xbar_random_zero_delays	18.040s	19.154us	1	1	100.00
		xbar_random_large_delays	25.534m	13.281ms	1	1	100.00
		xbar_random_slow_rsp	18.738m	6.528ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	41.200s	25.930us	1	1	100.00
		xbar_error_and_unmapped_addr	54.840s	110.711us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	3.105m	526.692us	1	1	100.00
		xbar_error_and_unmapped_addr	54.840s	110.711us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.834m	399.520us	1	1	100.00
		xbar_access_same_device_slow_rsp	53.042m	21.034ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.599m	243.056us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	14.012m	1.953ms	1	1	100.00
		xbar_stress_all_with_error	6.758m	1.177ms	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	2.285m	66.164us	1	1	100.00
		xbar_stress_all_with_reset_error	24.086m	2.463ms	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	12.283s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	12.958s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	11.755s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	13.787s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	11.698s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	13.708s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	14.383s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	12.190s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	11.198s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	15.336s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	11.659s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	11.929s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	11.507s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	1.190m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	1.022m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	1.260m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	1.007m		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	1.078m		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	1.044m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	1.139m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	1.076m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	1.080m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	1.170m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	58.424s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	1.010m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	1.079m		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	36.677s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	33.229s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	12.257s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	15.255s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	12.207s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	12.842s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	11.948s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	11.922s		0	1	0.00
		rom_e2e_asm_init_dev	11.617s		0	1	0.00
		rom_e2e_asm_init_prod	12.097s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.535s		0	1	0.00
		rom_e2e_asm_init_rma	12.168s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	12.846s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	11.689s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	12.301s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	12.149s		0	1	0.00
V2		TOTAL			63	205	30.73
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	6.119m	5.554ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	4.432m	5.153ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	12.167s		0	1	0.00
		rom_e2e_jtag_debug_dev	12.561s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.329s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	12.713s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	21.720m	11.954ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	42.007s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	18.299m	16.452ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	13.247s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	11.451s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	12.167s		0	1	0.00
		rom_e2e_jtag_debug_dev	12.561s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.329s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	11.501s		0	1	0.00
		rom_e2e_jtag_inject_dev	12.130s		0	1	0.00
		rom_e2e_jtag_inject_rma	12.101s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	11.564s		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	21.847m	15.094ms	1	1	100.00
		chip_sw_entropy_src_kat_test	4.622m	3.939ms	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	4.692m	5.086ms	1	1	100.00
		chip_plic_all_irqs_0	8.999m	6.356ms	1	1	100.00
		chip_plic_all_irqs_10	11.011m	7.098ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.638m	5.830ms	1	1	100.00
		chip_sw_dma_abort	4.685m	5.626ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	12.125s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	11.794s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	11.663s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	11.586s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	11.660s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	11.812s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	11.505s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	11.553s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	12.563s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	12.922s		0	1	0.00
		chip_sw_entropy_src_smoketest	4.127m	5.137ms	1	1	100.00
		chip_sw_mbx_smoketest	4.524m	5.784ms	1	1	100.00
		TOTAL			77	250	30.80

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.46781657677095939035422229497016016843414427197765904268970151719624515606493
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 119.752s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.97894372999072403228858971423955075060933126582123262368296061980134482484646
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 89.691s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.85590932041874249951117604218127382033481115190457151567338782435750157103071
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 87.625s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.99062940917747167774294562778065513139811999204656129462269399542483549911971
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 84.209s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.37662528327184791990141950059428226067634148340117394381502787567647332912920
Log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Target //sw/device/tests:uart_tx_rx_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (b853eb)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 80.249s, Critical Path: 0.00s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.9415202073612769283742884279784699067558298672846302411453569915407803592041
    Line 380, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.160001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.28052003454141999380658312509182822125626273856622943115443212118300621538130
    Line 396, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.7097801867233272507891475969023787373795283496067910397896740017765516079127
    Line 379, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.280001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.99809574848014739776327821915930502756676193344610109052902284305227853883631
    Line 380, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.31233277499849040762989570468776474303142727331694044563865398381344667994672
    Line 391, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 4 failures:

Test chip_sw_clkmgr_off_aes_trans has 1 failures.

0.chip_sw_clkmgr_off_aes_trans.33402488514890726787064831425591335799367442892938652686975739013811425959749
Line 402, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12026.976339 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.976339 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

0.chip_sw_clkmgr_off_hmac_trans.94263197823677407767378166362548103099102514518259936359830569238421668067915
Line 402, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12018.700307 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.700307 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_kmac_trans has 1 failures.

0.chip_sw_clkmgr_off_kmac_trans.60905266604920079863153847307461525866156283033740560383326968105908913504140
Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12026.835253 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.835253 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_otbn_trans has 1 failures.

0.chip_sw_clkmgr_off_otbn_trans.20408061900536851237995459780690611109253472796726671687088138872913543390363
Line 390, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12026.589878 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12026.589878 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.97967486913278083055982024658438158706869403091409843098932497340625589529281
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.81424252287033558582346230906247477502420754829562702056809498308657564798695
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.87050324161864016228465714300622232692141550258001702528774582224327901416333
    Line 133, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.3622312435527389587444065260516447109339386227906977054603355497766826851442
Line 415, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20018.445823 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20018.445823 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.92438485537872021163614466767381203278461439266838136390503518448973227559639
Line 412, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18026.931955 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18026.931955 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.14486519743797901982289689017385851810072970434305799308040633634565289116193
Line 401, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18026.995790 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18026.995790 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_*_key == get_otp_root_key() (* [*] vs * [*]) Expecting boot stage * key to equal creator root key (UDS) from OTP has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.18321449340003055944031085335240254122135137545685053802325501424527098985209
Line 420, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 9531.474531 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (5524227215909362865224469531144111588363857781128201362197990167646171967593561516181402704266424031070252196388051153250655819316452700868748790018169948 [0x6979dc33aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3ef2f6cc27f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 9531.474531 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.110026512813540719447804494438973596403798174970344956056611412038460436812916
Line 404, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 7532.107600 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:91) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed stage_0_key == get_otp_root_key() (4848727499761809370437351045495455807636132084597734446470773945979787922620450353041413302055270200637016289770453985379558933589098065363214708030921820 [0x5c941619aae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd3dac2a6e87f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c] vs 11215554652525030750439897942755197157874305238639658102584100640388816185692128121488765684043362451728722615066578775045707746854198728065777318205152348 [0xd6247d3baae844f2f7a7603fbfb6f3545b073c9def6c4889d8d3681ee5e09dd35072cdca7f1076d6800bd13c9a690428f1ac7bcc8c3d21c37136056170055c5c]) Expecting boot stage 0 key to equal creator root key (UDS) from OTP
  UVM_INFO @ 7532.107600 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47301) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.38794643999992305513708586067498365936704379681342184399855480835398956199594
Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 3806.984279 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47301) { a_addr: 'h30480000  a_data: 'hd0674058  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2d  a_opcode: 'h0  a_user: 'h26904  d_param: 'h0  d_source: 'h2d  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3806.984279 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.27766282211379392332432144913644385087013873419098396956888123149111238427834
Line 6262, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3620.298258 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@47301) { a_addr: 'h30480000  a_data: 'h32fbdf1f  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h14  a_opcode: 'h1  a_user: 'h248e4  d_param: 'h0  d_source: 'h14  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3620.298258 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.57476903164897561569095527021256385298282476483191150676294098174496909157056
    Line 1357, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.27592794426361342467997668432360096013129052388035236854635023529098897590230
    Line 453, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3492.912593 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3492.912593 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.88379377581496840420267655911733738992997741305248529592834598847884951268820
    Line 634, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 10048.025065 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:669)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 10048.025065 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.103882319206970641309153984961599274000394590975489062629001867282252894509199
    Line 401, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 3710.761412 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 3710.761412 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.109043262078528455878070678637660866452178416186835448875464946298328990518019
    Line 408, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 5455.089632 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 5455.089632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.54489547365194014696084647963145352374080016978652219002333637132710300301836
    Line 394, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 5416.969535 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 5416.969535 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_rnd_test_sim_dv(sw/device/tests/rv_core_ibex_rnd_test.c:94)] CHECK-fail: status_value == * has 1 failures:
- Test chip_sw_rv_core_ibex_rnd has 1 failures.
  - 0.chip_sw_rv_core_ibex_rnd.74656982023717276257216913461432465781052309326521980907271944632311684421936
    Line 387, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_rnd/latest/run.log
```
  UVM_ERROR @ 6205.875992 us: (sw_logger_if.sv:526) [rv_core_ibex_rnd_test_sim_dv(sw/device/tests/rv_core_ibex_rnd_test.c:94)] CHECK-fail: status_value == 0
  UVM_INFO @ 6205.875992 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.20237653206072136258729720953414193346256406003055752195961289127372969675028
    Line 390, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 5835.659674 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 5835.659674 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.44100219918415146972597777587289871214302171689110994984559967867171644464837
    Line 396, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.42030699700816876395524349019401001078707048483998116241498211342340699642850
    Line 232, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 4321.965480 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 4321.965480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.62699935280749882084184358813269646302163803590259033044594444854833097069192
    Line 378, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 14204.256864 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 14204.256864 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_rv_dm_lc_disabled has 1 failures.
  - 0.chip_rv_dm_lc_disabled.37924029423312949595974695393105413252721634828997961778898649189143584001557
    Line 235, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
```
  UVM_ERROR @ 7824.840189 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x406f0 read out mismatch
  UVM_INFO @ 7824.840189 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.106180444034808579276219798587397643409607246687849352948311096944791591575233
    Line 278, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 94
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.13474342320631663879035260184510623292121524359392232026129220188376070076053
    Line 389, in log /nightly/current_run/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 5626.304700 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 5626.304700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```