AES/MASKED Simulation Results

Wednesday October 22 2025 16:03:16 UTC

GitHub Revision: fc2d73b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	107.175us	1	1	100.00
V1	smoke	aes_smoke	6.000s	280.774us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	2.000s	67.684us	1	1	100.00
V1	csr_rw	aes_csr_rw	2.000s	60.835us	1	1	100.00
V1	csr_bit_bash	aes_csr_bit_bash	8.000s	1.221ms	1	1	100.00
V1	csr_aliasing	aes_csr_aliasing	2.000s	283.821us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	2.000s	65.813us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	2.000s	60.835us	1	1	100.00
		aes_csr_aliasing	2.000s	283.821us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	algorithm	aes_smoke	6.000s	280.774us	1	1	100.00
		aes_config_error	7.000s	1.125ms	1	1	100.00
		aes_stress	2.000s	80.325us	1	1	100.00
V2	key_length	aes_smoke	6.000s	280.774us	1	1	100.00
		aes_config_error	7.000s	1.125ms	1	1	100.00
		aes_stress	2.000s	80.325us	1	1	100.00
V2	back2back	aes_stress	2.000s	80.325us	1	1	100.00
		aes_b2b	17.000s	270.496us	1	1	100.00
V2	backpressure	aes_stress	2.000s	80.325us	1	1	100.00
V2	multi_message	aes_smoke	6.000s	280.774us	1	1	100.00
		aes_config_error	7.000s	1.125ms	1	1	100.00
		aes_stress	2.000s	80.325us	1	1	100.00
		aes_alert_reset	5.000s	106.486us	1	1	100.00
V2	failure_test	aes_man_cfg_err	2.000s	138.626us	1	1	100.00
		aes_config_error	7.000s	1.125ms	1	1	100.00
		aes_alert_reset	5.000s	106.486us	1	1	100.00
V2	trigger_clear_test	aes_clear	5.000s	1.395ms	1	1	100.00
V2	nist_test_vectors	aes_nist_vectors	8.000s	655.220us	1	1	100.00
V2	reset_recovery	aes_alert_reset	5.000s	106.486us	1	1	100.00
V2	stress	aes_stress	2.000s	80.325us	1	1	100.00
V2	sideload	aes_stress	2.000s	80.325us	1	1	100.00
		aes_sideload	3.000s	91.138us	1	1	100.00
V2	deinitialization	aes_deinit	4.000s	146.640us	1	1	100.00
V2	stress_all	aes_stress_all	15.000s	616.826us	1	1	100.00
V2	alert_test	aes_alert_test	2.000s	142.584us	1	1	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	3.000s	91.551us	1	1	100.00
V2	tl_d_illegal_access	aes_tl_errors	3.000s	91.551us	1	1	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	2.000s	67.684us	1	1	100.00
		aes_csr_rw	2.000s	60.835us	1	1	100.00
		aes_csr_aliasing	2.000s	283.821us	1	1	100.00
		aes_same_csr_outstanding	2.000s	152.463us	1	1	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	2.000s	67.684us	1	1	100.00
		aes_csr_rw	2.000s	60.835us	1	1	100.00
		aes_csr_aliasing	2.000s	283.821us	1	1	100.00
		aes_same_csr_outstanding	2.000s	152.463us	1	1	100.00
V2		TOTAL			13	13	100.00
V2S	reseeding	aes_reseed	5.000s	101.165us	1	1	100.00
V2S	fault_inject	aes_fi	3.000s	258.727us	1	1	100.00
		aes_control_fi	2.000s	78.668us	1	1	100.00
		aes_cipher_fi	27.000s	10.020ms	0	1	0.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	2.000s	84.346us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	2.000s	84.346us	1	1	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	2.000s	84.346us	1	1	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	2.000s	84.346us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	3.000s	658.839us	1	1	100.00
V2S	tl_intg_err	aes_sec_cm	4.000s	1.425ms	1	1	100.00
		aes_tl_intg_err	2.000s	612.323us	1	1	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	2.000s	612.323us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	5.000s	106.486us	1	1	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	2.000s	84.346us	1	1	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	6.000s	280.774us	1	1	100.00
		aes_stress	2.000s	80.325us	1	1	100.00
		aes_alert_reset	5.000s	106.486us	1	1	100.00
		aes_core_fi	2.000s	103.370us	1	1	100.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	2.000s	84.346us	1	1	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	2.000s	99.370us	1	1	100.00
		aes_stress	2.000s	80.325us	1	1	100.00
V2S	sec_cm_key_sideload	aes_stress	2.000s	80.325us	1	1	100.00
		aes_sideload	3.000s	91.138us	1	1	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	2.000s	99.370us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	2.000s	99.370us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	2.000s	99.370us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	2.000s	99.370us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	2.000s	99.370us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	2.000s	80.325us	1	1	100.00
V2S	sec_cm_key_masking	aes_stress	2.000s	80.325us	1	1	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	3.000s	258.727us	1	1	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	3.000s	258.727us	1	1	100.00
		aes_control_fi	2.000s	78.668us	1	1	100.00
		aes_cipher_fi	27.000s	10.020ms	0	1	0.00
		aes_ctr_fi	2.000s	53.449us	1	1	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	3.000s	258.727us	1	1	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	3.000s	258.727us	1	1	100.00
		aes_control_fi	2.000s	78.668us	1	1	100.00
		aes_cipher_fi	27.000s	10.020ms	0	1	0.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	27.000s	10.020ms	0	1	0.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	3.000s	258.727us	1	1	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	3.000s	258.727us	1	1	100.00
		aes_control_fi	2.000s	78.668us	1	1	100.00
		aes_ctr_fi	2.000s	53.449us	1	1	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	3.000s	258.727us	1	1	100.00
		aes_control_fi	2.000s	78.668us	1	1	100.00
		aes_cipher_fi	27.000s	10.020ms	0	1	0.00
		aes_ctr_fi	2.000s	53.449us	1	1	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	5.000s	106.486us	1	1	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	3.000s	258.727us	1	1	100.00
		aes_control_fi	2.000s	78.668us	1	1	100.00
		aes_cipher_fi	27.000s	10.020ms	0	1	0.00
		aes_ctr_fi	2.000s	53.449us	1	1	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	3.000s	258.727us	1	1	100.00
		aes_control_fi	2.000s	78.668us	1	1	100.00
		aes_cipher_fi	27.000s	10.020ms	0	1	0.00
		aes_ctr_fi	2.000s	53.449us	1	1	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	3.000s	258.727us	1	1	100.00
		aes_control_fi	2.000s	78.668us	1	1	100.00
		aes_ctr_fi	2.000s	53.449us	1	1	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	3.000s	258.727us	1	1	100.00
		aes_control_fi	2.000s	78.668us	1	1	100.00
		aes_cipher_fi	27.000s	10.020ms	0	1	0.00
V2S		TOTAL			10	11	90.91
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	19.000s	1.719ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			30	32	93.75

Failure Buckets

• UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 1 failures:

  • Test aes_cipher_fi has 1 failures.

    • 0.aes_cipher_fi.107369200777949359181853360842840845467759046028791288748145499008795135775016
      Line 134, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_cipher_fi/latest/run.log

        UVM_FATAL @ 10019858259 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
        UVM_INFO @ 10019858259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.92744241228582204962707362033487585201416602927615022081687090037144935143588
      Line 602, in log /nightly/current_run/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1719166928 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1719166928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---