DMA Simulation Results

Wednesday October 22 2025 16:03:16 UTC

GitHub Revision: fc2d73b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	4.000s	458.354us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	5.000s	516.114us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	4.000s	1.009ms	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	2.000s	29.236us	1	1	100.00
V1	csr_rw	dma_csr_rw	2.000s	18.883us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	6.000s	1.020ms	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	4.000s	291.629us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	2.000s	26.345us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	2.000s	18.883us	1	1	100.00
		dma_csr_aliasing	4.000s	291.629us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.183m	10.635ms	1	1	100.00
V2	dma_memory_tl_error	dma_memory_stress	2.550m	14.675ms	1	1	100.00
V2	dma_handshake_tl_error	dma_handshake_stress	6.917m	42.129ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	6.917m	42.129ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	2.550m	14.675ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	2.633m	13.936ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	6.917m	42.129ms	1	1	100.00
V2	dma_abort	dma_abort	2.000s	92.338us	1	1	100.00
V2	dma_stress_all	dma_stress_all	1.800m	9.746ms	1	1	100.00
V2	alert_test	dma_alert_test	1.000s	14.302us	1	1	100.00
V2	intr_test	dma_intr_test	1.000s	23.215us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	3.000s	128.600us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	3.000s	128.600us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	2.000s	29.236us	1	1	100.00
		dma_csr_rw	2.000s	18.883us	1	1	100.00
		dma_csr_aliasing	4.000s	291.629us	1	1	100.00
		dma_same_csr_outstanding	2.000s	69.599us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	2.000s	29.236us	1	1	100.00
		dma_csr_rw	2.000s	18.883us	1	1	100.00
		dma_csr_aliasing	4.000s	291.629us	1	1	100.00
		dma_same_csr_outstanding	2.000s	69.599us	1	1	100.00
V2		TOTAL			10	10	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	14.000s	73.215us	1	1	100.00
		dma_generic_stress	2.633m	13.936ms	1	1	100.00
		dma_handshake_stress	6.917m	42.129ms	1	1	100.00
V2S	dma_config_lock	dma_config_lock	6.000s	3.647ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	3.000s	1.216ms	1	1	100.00
		dma_sec_cm	1.000s	10.702us	1	1	100.00
V2S		TOTAL			4	4	100.00
	Unmapped tests	dma_short_transfer	51.000s	11.357ms	1	1	100.00
		dma_longer_transfer	3.000s	106.066us	1	1	100.00
		dma_stress_all_with_rand_reset	12.000s	3.465ms	0	1	0.00
		TOTAL			24	25	96.00

Failure Buckets

• UVM_ERROR @ *ps: (cip_base_vseq.sv:1230) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test dma_stress_all_with_rand_reset has 1 failures.

    • 0.dma_stress_all_with_rand_reset.17250288331445608183065798118913054727130284082204601280803419420998918265618
      Line 123, in log /nightly/current_run/scratch/master/dma-sim-xcelium/0.dma_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3465290528ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.dma_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3465290528ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---