EDN Simulation Results

Wednesday October 22 2025 16:03:16 UTC

GitHub Revision: fc2d73b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.260s	29.182us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.820s	30.031us	1	1	100.00
V1	csr_rw	edn_csr_rw	0.760s	40.055us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	2.320s	116.042us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.140s	26.695us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	0.980s	34.781us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.760s	40.055us	1	1	100.00
		edn_csr_aliasing	1.140s	26.695us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	0.930s	59.953us	1	1	100.00
V2	csrng_commands	edn_genbits	0.930s	59.953us	1	1	100.00
V2	genbits	edn_genbits	0.930s	59.953us	1	1	100.00
V2	interrupts	edn_intr	0.830s	35.430us	1	1	100.00
V2	alerts	edn_alert	0.960s	23.786us	1	1	100.00
V2	errs	edn_err	0.940s	45.195us	1	1	100.00
V2	disable	edn_disable	0.990s	20.604us	1	1	100.00
		edn_disable_auto_req_mode	1.140s	101.548us	1	1	100.00
V2	stress_all	edn_stress_all	1.600s	810.839us	1	1	100.00
V2	intr_test	edn_intr_test	0.870s	14.311us	1	1	100.00
V2	alert_test	edn_alert_test	0.930s	32.123us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	1.500s	68.532us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	1.500s	68.532us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.820s	30.031us	1	1	100.00
		edn_csr_rw	0.760s	40.055us	1	1	100.00
		edn_csr_aliasing	1.140s	26.695us	1	1	100.00
		edn_same_csr_outstanding	1.010s	27.103us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.820s	30.031us	1	1	100.00
		edn_csr_rw	0.760s	40.055us	1	1	100.00
		edn_csr_aliasing	1.140s	26.695us	1	1	100.00
		edn_same_csr_outstanding	1.010s	27.103us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	6.020s	2.031ms	1	1	100.00
		edn_tl_intg_err	1.350s	94.183us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.870s	18.626us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	0.960s	23.786us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.020s	2.031ms	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.020s	2.031ms	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	6.020s	2.031ms	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.020s	2.031ms	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	0.960s	23.786us	1	1	100.00
		edn_sec_cm	6.020s	2.031ms	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	0.960s	23.786us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	1.350s	94.183us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	28.070s	1.772ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00