ENTROPY_SRC/RNG_16BITS Simulation Results

Wednesday October 22 2025 16:03:16 UTC

GitHub Revision: fc2d73b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 2.000s 57.940us 1 1 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 3.000s 41.968us 1 1 100.00
V1 csr_rw entropy_src_csr_rw 1.000s 18.342us 1 1 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 12.000s 2.648ms 1 1 100.00
V1 csr_aliasing entropy_src_csr_aliasing 4.000s 966.813us 1 1 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 3.000s 225.489us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 1.000s 18.342us 1 1 100.00
entropy_src_csr_aliasing 4.000s 966.813us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware entropy_src_smoke 2.000s 57.940us 1 1 100.00
entropy_src_rng 8.617m 20.046ms 1 1 100.00
entropy_src_fw_ov 4.117m 20.076ms 1 1 100.00
V2 firmware_mode entropy_src_fw_ov 4.117m 20.076ms 1 1 100.00
V2 rng_mode entropy_src_rng 8.617m 20.046ms 1 1 100.00
V2 rng_max_rate entropy_src_rng_max_rate 1.217m 14.273ms 1 1 100.00
V2 health_checks entropy_src_rng 8.617m 20.046ms 1 1 100.00
V2 conditioning entropy_src_rng 8.617m 20.046ms 1 1 100.00
V2 interrupts entropy_src_rng 8.617m 20.046ms 1 1 100.00
entropy_src_intr 16.000s 1.847ms 1 1 100.00
V2 alerts entropy_src_rng 8.617m 20.046ms 1 1 100.00
entropy_src_functional_alerts 6.000s 354.437us 1 1 100.00
V2 stress_all entropy_src_stress_all 4.033m 13.259ms 1 1 100.00
V2 functional_errors entropy_src_functional_errors 2.000s 111.713us 1 1 100.00
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 5.000s 145.794us 1 1 100.00
V2 intr_test entropy_src_intr_test 2.000s 64.261us 1 1 100.00
V2 alert_test entropy_src_alert_test 2.000s 32.841us 1 1 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 4.000s 486.392us 1 1 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 4.000s 486.392us 1 1 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 3.000s 41.968us 1 1 100.00
entropy_src_csr_rw 1.000s 18.342us 1 1 100.00
entropy_src_csr_aliasing 4.000s 966.813us 1 1 100.00
entropy_src_same_csr_outstanding 4.000s 254.024us 1 1 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 3.000s 41.968us 1 1 100.00
entropy_src_csr_rw 1.000s 18.342us 1 1 100.00
entropy_src_csr_aliasing 4.000s 966.813us 1 1 100.00
entropy_src_same_csr_outstanding 4.000s 254.024us 1 1 100.00
V2 TOTAL 12 12 100.00
V2S tl_intg_err entropy_src_sec_cm 3.000s 95.789us 1 1 100.00
entropy_src_tl_intg_err 7.000s 192.788us 1 1 100.00
V2S sec_cm_config_regwen entropy_src_rng 8.617m 20.046ms 1 1 100.00
entropy_src_cfg_regwen 2.000s 20.230us 1 1 100.00
V2S sec_cm_config_mubi entropy_src_rng 8.617m 20.046ms 1 1 100.00
V2S sec_cm_config_redun entropy_src_rng 8.617m 20.046ms 1 1 100.00
V2S sec_cm_intersig_mubi entropy_src_rng 8.617m 20.046ms 1 1 100.00
entropy_src_fw_ov 4.117m 20.076ms 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 2.000s 111.713us 1 1 100.00
entropy_src_sec_cm 3.000s 95.789us 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 2.000s 111.713us 1 1 100.00
entropy_src_sec_cm 3.000s 95.789us 1 1 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 8.617m 20.046ms 1 1 100.00
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 2.000s 111.713us 1 1 100.00
entropy_src_sec_cm 3.000s 95.789us 1 1 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 2.000s 111.713us 1 1 100.00
entropy_src_sec_cm 3.000s 95.789us 1 1 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 2.000s 111.713us 1 1 100.00
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 6.000s 354.437us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 7.000s 192.788us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 1.900m 17.092ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 22 22 100.00