HMAC Simulation Results

Wednesday October 22 2025 16:03:16 UTC

GitHub Revision: fc2d73b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 7.600s 255.733us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.030s 147.918us 1 1 100.00
V1 csr_rw hmac_csr_rw 0.890s 85.241us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 3.960s 372.554us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 3.900s 299.945us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 2.140s 126.269us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.890s 85.241us 1 1 100.00
hmac_csr_aliasing 3.900s 299.945us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 11.960s 3.576ms 1 1 100.00
V2 back_pressure hmac_back_pressure 48.840s 6.685ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.500s 373.939us 1 1 100.00
hmac_test_sha384_vectors 6.474m 57.625ms 1 1 100.00
hmac_test_sha512_vectors 19.510s 666.574us 1 1 100.00
hmac_test_hmac256_vectors 7.730s 249.710us 1 1 100.00
hmac_test_hmac384_vectors 7.150s 1.168ms 1 1 100.00
hmac_test_hmac512_vectors 8.010s 469.596us 1 1 100.00
V2 burst_wr hmac_burst_wr 17.840s 1.870ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 13.300s 797.522us 1 1 100.00
V2 error hmac_error 1.213m 7.814ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 10.160s 1.257ms 1 1 100.00
V2 save_and_restore hmac_smoke 7.600s 255.733us 1 1 100.00
hmac_long_msg 11.960s 3.576ms 1 1 100.00
hmac_back_pressure 48.840s 6.685ms 1 1 100.00
hmac_datapath_stress 13.300s 797.522us 1 1 100.00
hmac_burst_wr 17.840s 1.870ms 1 1 100.00
hmac_stress_all 16.343m 16.833ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 7.600s 255.733us 1 1 100.00
hmac_long_msg 11.960s 3.576ms 1 1 100.00
hmac_back_pressure 48.840s 6.685ms 1 1 100.00
hmac_datapath_stress 13.300s 797.522us 1 1 100.00
hmac_wipe_secret 10.160s 1.257ms 1 1 100.00
hmac_test_sha256_vectors 8.500s 373.939us 1 1 100.00
hmac_test_sha384_vectors 6.474m 57.625ms 1 1 100.00
hmac_test_sha512_vectors 19.510s 666.574us 1 1 100.00
hmac_test_hmac256_vectors 7.730s 249.710us 1 1 100.00
hmac_test_hmac384_vectors 7.150s 1.168ms 1 1 100.00
hmac_test_hmac512_vectors 8.010s 469.596us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 7.600s 255.733us 1 1 100.00
hmac_long_msg 11.960s 3.576ms 1 1 100.00
hmac_back_pressure 48.840s 6.685ms 1 1 100.00
hmac_datapath_stress 13.300s 797.522us 1 1 100.00
hmac_burst_wr 17.840s 1.870ms 1 1 100.00
hmac_error 1.213m 7.814ms 1 1 100.00
hmac_wipe_secret 10.160s 1.257ms 1 1 100.00
hmac_test_sha256_vectors 8.500s 373.939us 1 1 100.00
hmac_test_sha384_vectors 6.474m 57.625ms 1 1 100.00
hmac_test_sha512_vectors 19.510s 666.574us 1 1 100.00
hmac_test_hmac256_vectors 7.730s 249.710us 1 1 100.00
hmac_test_hmac384_vectors 7.150s 1.168ms 1 1 100.00
hmac_test_hmac512_vectors 8.010s 469.596us 1 1 100.00
hmac_stress_all 16.343m 16.833ms 1 1 100.00
V2 stress_all hmac_stress_all 16.343m 16.833ms 1 1 100.00
V2 alert_test hmac_alert_test 0.640s 25.713us 1 1 100.00
V2 intr_test hmac_intr_test 0.780s 14.769us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.970s 780.584us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.970s 780.584us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.030s 147.918us 1 1 100.00
hmac_csr_rw 0.890s 85.241us 1 1 100.00
hmac_csr_aliasing 3.900s 299.945us 1 1 100.00
hmac_same_csr_outstanding 1.010s 57.886us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.030s 147.918us 1 1 100.00
hmac_csr_rw 0.890s 85.241us 1 1 100.00
hmac_csr_aliasing 3.900s 299.945us 1 1 100.00
hmac_same_csr_outstanding 1.010s 57.886us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.080s 156.871us 1 1 100.00
hmac_tl_intg_err 2.300s 171.028us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.300s 171.028us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 7.600s 255.733us 1 1 100.00
V3 stress_reset hmac_stress_reset 5.820s 300.928us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 2.594m 3.585ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.070s 58.030us 1 1 100.00
TOTAL 28 28 100.00