I2C Simulation Results

Wednesday October 22 2025 16:03:16 UTC

GitHub Revision: fc2d73b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	46.980s	5.469ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	8.410s	1.747ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.010s	45.676us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.050s	50.840us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.620s	702.819us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.390s	77.317us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.400s	190.372us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.050s	50.840us	1	1	100.00
		i2c_csr_aliasing	1.390s	77.317us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	1.060s	41.230us	0	1	0.00
V2	host_stress_all	i2c_host_stress_all	8.367m	34.894ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	3.285m	96.505ms	1	1	100.00
V2	host_override	i2c_host_override	0.850s	25.680us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	3.194m	5.374ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	57.830s	1.338ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	0.970s	278.016us	1	1	100.00
		i2c_host_fifo_fmt_empty	4.200s	688.586us	1	1	100.00
		i2c_host_fifo_reset_rx	2.940s	261.764us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.813m	2.557ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	10.440s	6.772ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.010s	87.840us	0	1	0.00
V2	target_glitch	i2c_target_glitch	3.450s	505.576us	0	1	0.00
V2	target_stress_all	i2c_target_stress_all	1.576m	18.992ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.870s	2.088ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	16.040s	2.465ms	1	1	100.00
		i2c_target_intr_smoke	5.420s	2.534ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.350s	208.074us	1	1	100.00
		i2c_target_fifo_reset_tx	1.370s	394.676us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	29.320s	38.663ms	1	1	100.00
		i2c_target_stress_rd	16.040s	2.465ms	1	1	100.00
		i2c_target_intr_stress_wr	13.800s	10.013ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.350s	2.964ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	24.760s	4.105ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	2.800s	4.518ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	5.180s	10.269ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	1.560s	388.628us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.010s	443.341us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	3.285m	96.505ms	1	1	100.00
		i2c_host_perf_precise	12.490s	415.061us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	10.440s	6.772ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	6.060s	595.962us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.130s	1.085ms	1	1	100.00
		i2c_target_nack_acqfull_addr	1.970s	1.985ms	1	1	100.00
		i2c_target_nack_txstretch	1.280s	2.315ms	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	12.780s	2.243ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	1.870s	447.528us	1	1	100.00
V2	alert_test	i2c_alert_test	0.860s	15.437us	1	1	100.00
V2	intr_test	i2c_intr_test	0.940s	19.302us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	1.220s	50.099us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	1.220s	50.099us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.010s	45.676us	1	1	100.00
		i2c_csr_rw	1.050s	50.840us	1	1	100.00
		i2c_csr_aliasing	1.390s	77.317us	1	1	100.00
		i2c_same_csr_outstanding	0.820s	114.582us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.010s	45.676us	1	1	100.00
		i2c_csr_rw	1.050s	50.840us	1	1	100.00
		i2c_csr_aliasing	1.390s	77.317us	1	1	100.00
		i2c_same_csr_outstanding	0.820s	114.582us	1	1	100.00
V2		TOTAL			32	38	84.21
V2S	tl_intg_err	i2c_tl_intg_err	2.660s	548.286us	1	1	100.00
		i2c_sec_cm	1.000s	92.118us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.660s	548.286us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	11.870s	1.372ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.250s	338.570us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	8.260s	1.441ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			41	50	82.00

Failure Buckets

• UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between has 2 failures:

  • Test i2c_host_error_intr has 1 failures.

    • 0.i2c_host_error_intr.100496493720114362989883019519462531034160805713091364482867011314907965541296
      Line 91, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_error_intr/latest/run.log

        UVM_ERROR @  41230057 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @  41230057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.56189728179776987155299975891034672204744660956677357344490124267027939588544
      Line 92, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1440809008 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
        UVM_INFO @ 1440809008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.105478367979308469744714446680487027576810612179147296094923629807143001876251
      Line 127, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 34893794868 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @4475067
      

• UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between has 1 failures:

  • Test i2c_target_glitch has 1 failures.

    • 0.i2c_target_glitch.7472965620501878842069340451591641709569019068060975748340009701329117210649
      Line 81, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_glitch/latest/run.log

        UVM_ERROR @ 505575670 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
        UVM_INFO @ 505575670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.54273978160273564488059974758045512603905026996286664362370435205191833042568
      Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

            Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
        UVM_ERROR @ 338569690 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
        UVM_INFO @ 338569690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.68532534303989932215945157227613539161029751514911751280334131628160748455312
      Line 76, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10268660189 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10268660189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:1229) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.91559664038850812570501686628325148055722914548718931198629950330798725068202
      Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1371622288 ps: (cip_base_vseq.sv:1229) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1371622288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.5581866480294244875443129370464113485145081848098607461969055048301127396109
      Line 84, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @  87840471 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
        --> EXP:
        ---------------------------------------------------
        Name            Type                Size  Value
        ---------------------------------------------------
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:

  • Test i2c_target_nack_txstretch has 1 failures.

    • 0.i2c_target_nack_txstretch.67675184301531322925428352698168461215215510836856991188501920789137867500668
      Line 75, in log /nightly/current_run/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log

        UVM_ERROR @ 2315043370 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
        UVM_INFO @ 2315043370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---