| V1 |
smoke |
kmac_smoke |
3.310s |
131.454us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
kmac_csr_hw_reset |
0.950s |
16.367us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
kmac_csr_rw |
1.110s |
61.514us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
kmac_csr_bit_bash |
5.890s |
299.680us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
kmac_csr_aliasing |
3.270s |
292.757us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
kmac_csr_mem_rw_with_rand_reset |
1.430s |
176.685us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
kmac_csr_rw |
1.110s |
61.514us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
3.270s |
292.757us |
1 |
1 |
100.00 |
| V1 |
mem_walk |
kmac_mem_walk |
0.830s |
22.267us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
kmac_mem_partial_access |
1.440s |
44.200us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
long_msg_and_output |
kmac_long_msg_and_output |
25.669m |
87.263ms |
1 |
1 |
100.00 |
| V2 |
burst_write |
kmac_burst_write |
8.389m |
24.469ms |
1 |
1 |
100.00 |
| V2 |
test_vectors |
kmac_test_vectors_sha3_224 |
32.201m |
140.296ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_256 |
28.920s |
1.803ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_384 |
18.562m |
26.032ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_512 |
13.606m |
35.740ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_128 |
35.795m |
300.880ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_256 |
1.830m |
7.568ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac |
3.760s |
237.299us |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac_xof |
2.680s |
100.553us |
1 |
1 |
100.00 |
| V2 |
sideload |
kmac_sideload |
2.590s |
62.138us |
1 |
1 |
100.00 |
| V2 |
app |
kmac_app |
3.745m |
5.221ms |
1 |
1 |
100.00 |
| V2 |
app_with_partial_data |
kmac_app_with_partial_data |
1.785m |
40.026ms |
1 |
1 |
100.00 |
| V2 |
entropy_refresh |
kmac_entropy_refresh |
49.290s |
5.220ms |
1 |
1 |
100.00 |
| V2 |
error |
kmac_error |
2.181m |
2.399ms |
1 |
1 |
100.00 |
| V2 |
key_error |
kmac_key_error |
12.730s |
1.635ms |
1 |
1 |
100.00 |
| V2 |
sideload_invalid |
kmac_sideload_invalid |
6.100s |
337.471us |
1 |
1 |
100.00 |
| V2 |
edn_timeout_error |
kmac_edn_timeout_error |
1.170s |
38.298us |
1 |
1 |
100.00 |
| V2 |
entropy_mode_error |
kmac_entropy_mode_error |
1.200s |
42.557us |
1 |
1 |
100.00 |
| V2 |
entropy_ready_error |
kmac_entropy_ready_error |
22.780s |
5.517ms |
1 |
1 |
100.00 |
| V2 |
lc_escalation |
kmac_lc_escalation |
1.310s |
35.316us |
1 |
1 |
100.00 |
| V2 |
stress_all |
kmac_stress_all |
20.558m |
71.716ms |
1 |
1 |
100.00 |
| V2 |
intr_test |
kmac_intr_test |
1.020s |
46.829us |
1 |
1 |
100.00 |
| V2 |
alert_test |
kmac_alert_test |
1.010s |
20.226us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
kmac_tl_errors |
1.980s |
487.637us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
kmac_tl_errors |
1.980s |
487.637us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
kmac_csr_hw_reset |
0.950s |
16.367us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
1.110s |
61.514us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
3.270s |
292.757us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
2.060s |
225.992us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
kmac_csr_hw_reset |
0.950s |
16.367us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
1.110s |
61.514us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
3.270s |
292.757us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
2.060s |
225.992us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
26 |
26 |
100.00 |
| V2S |
shadow_reg_update_error |
kmac_shadow_reg_errors |
1.520s |
63.039us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
kmac_shadow_reg_errors |
1.520s |
63.039us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
kmac_shadow_reg_errors |
1.520s |
63.039us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
kmac_shadow_reg_errors |
1.520s |
63.039us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
kmac_shadow_reg_errors_with_csr_rw |
3.260s |
155.750us |
1 |
1 |
100.00 |
| V2S |
tl_intg_err |
kmac_sec_cm |
29.360s |
4.873ms |
1 |
1 |
100.00 |
|
|
kmac_tl_intg_err |
1.960s |
110.297us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
kmac_tl_intg_err |
1.960s |
110.297us |
1 |
1 |
100.00 |
| V2S |
sec_cm_lc_escalate_en_intersig_mubi |
kmac_lc_escalation |
1.310s |
35.316us |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_key_key_masking |
kmac_smoke |
3.310s |
131.454us |
1 |
1 |
100.00 |
| V2S |
sec_cm_key_sideload |
kmac_sideload |
2.590s |
62.138us |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_shadow |
kmac_shadow_reg_errors |
1.520s |
63.039us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_sparse |
kmac_sec_cm |
29.360s |
4.873ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_ctr_redun |
kmac_sec_cm |
29.360s |
4.873ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_packer_ctr_redun |
kmac_sec_cm |
29.360s |
4.873ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_regwen |
kmac_smoke |
3.310s |
131.454us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_global_esc |
kmac_lc_escalation |
1.310s |
35.316us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_local_esc |
kmac_sec_cm |
29.360s |
4.873ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_absorbed_ctrl_mubi |
kmac_mubi |
2.852m |
4.343ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_cmd_ctrl_sparse |
kmac_smoke |
3.310s |
131.454us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
5 |
5 |
100.00 |
| V3 |
stress_all_with_rand_reset |
kmac_stress_all_with_rand_reset |
10.540s |
808.417us |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
40 |
40 |
100.00 |