fc2d73b| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 42.000s | 3.224ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 2.000s | 47.259us | 1 | 1 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 1.000s | 34.969us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 3.000s | 113.794us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 1.000s | 60.858us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 3.000s | 84.623us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 1.000s | 34.969us | 1 | 1 | 100.00 |
| mbx_csr_aliasing | 1.000s | 60.858us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 6 | 6 | 100.00 | |||
| V2 | mbx_stress | mbx_stress | 23.000s | 3.740ms | 1 | 1 | 100.00 |
| V2 | mbx_max_activity | mbx_stress_zero_delays | 2.000s | 24.928us | 0 | 1 | 0.00 |
| V2 | mbx_imbx_oob | mbx_imbx_oob | 22.000s | 4.687ms | 1 | 1 | 100.00 |
| V2 | mbx_doe_intr_msg | mbx_doe_intr_msg | 18.000s | 536.200us | 1 | 1 | 100.00 |
| V2 | alert_test | mbx_alert_test | 1.000s | 15.727us | 1 | 1 | 100.00 |
| V2 | intr_test | mbx_intr_test | 1.000s | 47.310us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 2.000s | 129.568us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 2.000s | 129.568us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 2.000s | 47.259us | 1 | 1 | 100.00 |
| mbx_csr_rw | 1.000s | 34.969us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 1.000s | 60.858us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 2.000s | 154.302us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 2.000s | 47.259us | 1 | 1 | 100.00 |
| mbx_csr_rw | 1.000s | 34.969us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 1.000s | 60.858us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 2.000s | 154.302us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 7 | 8 | 87.50 | |||
| V2S | tl_intg_err | mbx_tl_intg_err | 3.000s | 1.405ms | 1 | 1 | 100.00 |
| mbx_sec_cm | 1.000s | 13.478us | 1 | 1 | 100.00 | ||
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| TOTAL | 15 | 16 | 93.75 |
UVM_ERROR (mbx_scoreboard.sv:537) [scoreboard] Check failed m_ib_data_q.size() != * (* [*] vs * [*]) No write data in WDATA register has 1 failures:
0.mbx_stress_zero_delays.111239117561048788305739500348106452324235094784209022730597444018395418069730
Line 86, in log /nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress_zero_delays/latest/run.log
UVM_ERROR @ 24928417 ps: (mbx_scoreboard.sv:537) [uvm_test_top.env.scoreboard] Check failed m_ib_data_q.size() != 0 (0 [0x0] vs 0 [0x0]) No write data in WDATA register
UVM_INFO @ 24928417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---