ROM_CTRL/32KB Simulation Results

Wednesday October 22 2025 16:03:16 UTC

GitHub Revision: fc2d73b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	4.820s	461.429us	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	6.270s	538.620us	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	4.320s	333.639us	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	3.800s	130.122us	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	3.880s	538.355us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	4.880s	176.430us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	4.320s	333.639us	1	1	100.00
		rom_ctrl_csr_aliasing	3.880s	538.355us	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	5.120s	535.187us	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	3.510s	211.567us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	5.330s	181.285us	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	13.260s	467.466us	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	7.880s	302.123us	1	1	100.00
V2	alert_test	rom_ctrl_alert_test	3.990s	294.458us	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	5.810s	220.372us	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	5.810s	220.372us	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	6.270s	538.620us	1	1	100.00
		rom_ctrl_csr_rw	4.320s	333.639us	1	1	100.00
		rom_ctrl_csr_aliasing	3.880s	538.355us	1	1	100.00
		rom_ctrl_same_csr_outstanding	5.380s	176.131us	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	6.270s	538.620us	1	1	100.00
		rom_ctrl_csr_rw	4.320s	333.639us	1	1	100.00
		rom_ctrl_csr_aliasing	3.880s	538.355us	1	1	100.00
		rom_ctrl_same_csr_outstanding	5.380s	176.131us	1	1	100.00
V2		TOTAL			6	6	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	1.256m	2.398ms	1	1	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	20.050s	3.184ms	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	2.043m	1.474ms	0	1	0.00
		rom_ctrl_tl_intg_err	24.150s	2.641ms	1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	2.043m	1.474ms	0	1	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	2.043m	1.474ms	0	1	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.256m	2.398ms	1	1	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.256m	2.398ms	1	1	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.256m	2.398ms	1	1	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.256m	2.398ms	1	1	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.256m	2.398ms	1	1	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	2.043m	1.474ms	0	1	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	2.043m	1.474ms	0	1	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	4.820s	461.429us	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	4.820s	461.429us	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	4.820s	461.429us	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	24.150s	2.641ms	1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	1.256m	2.398ms	1	1	100.00
		rom_ctrl_kmac_err_chk	7.880s	302.123us	1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	1.256m	2.398ms	1	1	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	1.256m	2.398ms	1	1	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	1.256m	2.398ms	1	1	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	20.050s	3.184ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	2.043m	1.474ms	0	1	0.00
V2S		TOTAL			3	4	75.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	5.413m	3.836ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			18	19	94.74

Failure Buckets

• Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))' has 1 failures:
  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.48751541779131956260177926722343836655100905785367511142142073198340245869658
      Line 107, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 26444058ps failed at 26444058ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 26454367ps failed at 26454367ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'