ROM_CTRL/64KB Simulation Results

Wednesday October 22 2025 16:03:16 UTC

GitHub Revision: fc2d73b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	7.420s	223.992us	1	1	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	11.050s	1.287ms	1	1	100.00
V1	csr_rw	rom_ctrl_csr_rw	6.710s	2.093ms	1	1	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	6.600s	1.581ms	1	1	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	8.910s	556.576us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	8.480s	319.562us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	6.710s	2.093ms	1	1	100.00
		rom_ctrl_csr_aliasing	8.910s	556.576us	1	1	100.00
V1	mem_walk	rom_ctrl_mem_walk	8.260s	291.047us	1	1	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	8.150s	444.047us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	6.600s	733.644us	1	1	100.00
V2	stress_all	rom_ctrl_stress_all	34.100s	2.109ms	1	1	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	25.310s	547.806us	1	1	100.00
V2	alert_test	rom_ctrl_alert_test	9.650s	376.564us	1	1	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	9.240s	642.270us	1	1	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	9.240s	642.270us	1	1	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	11.050s	1.287ms	1	1	100.00
		rom_ctrl_csr_rw	6.710s	2.093ms	1	1	100.00
		rom_ctrl_csr_aliasing	8.910s	556.576us	1	1	100.00
		rom_ctrl_same_csr_outstanding	6.410s	726.234us	1	1	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	11.050s	1.287ms	1	1	100.00
		rom_ctrl_csr_rw	6.710s	2.093ms	1	1	100.00
		rom_ctrl_csr_aliasing	8.910s	556.576us	1	1	100.00
		rom_ctrl_same_csr_outstanding	6.410s	726.234us	1	1	100.00
V2		TOTAL			6	6	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	2.633m	23.656ms	1	1	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	40.580s	13.910ms	1	1	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	4.045m	2.491ms	0	1	0.00
		rom_ctrl_tl_intg_err	51.570s	383.934us	1	1	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	4.045m	2.491ms	0	1	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	4.045m	2.491ms	0	1	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.633m	23.656ms	1	1	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.633m	23.656ms	1	1	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.633m	23.656ms	1	1	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.633m	23.656ms	1	1	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.633m	23.656ms	1	1	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	4.045m	2.491ms	0	1	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	4.045m	2.491ms	0	1	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	7.420s	223.992us	1	1	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	7.420s	223.992us	1	1	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	7.420s	223.992us	1	1	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	51.570s	383.934us	1	1	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.633m	23.656ms	1	1	100.00
		rom_ctrl_kmac_err_chk	25.310s	547.806us	1	1	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	2.633m	23.656ms	1	1	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.633m	23.656ms	1	1	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	2.633m	23.656ms	1	1	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	40.580s	13.910ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	4.045m	2.491ms	0	1	0.00
V2S		TOTAL			3	4	75.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	2.431m	5.373ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			18	19	94.74

Failure Buckets

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 1 failures:
  • Test rom_ctrl_sec_cm has 1 failures.

    • 0.rom_ctrl_sec_cm.76203754534549987369383050324319486053991497513904860732659790456243149228058
      Line 106, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 6523969ps failed at 6523969ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 6582793ps failed at 6582793ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'