RV_TIMER Simulation Results

Wednesday October 22 2025 16:03:16 UTC

GitHub Revision: fc2d73b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.350s	508.506us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.750s	50.399us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.800s	13.012us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.090s	294.726us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.890s	20.213us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.090s	43.312us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.800s	13.012us	1	1	100.00
		rv_timer_csr_aliasing	0.890s	20.213us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	0.850s	676.697us	0	1	0.00
V2	disabled	rv_timer_disabled	1.180s	1.427ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	5.617m	1.058s	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	5.617m	1.058s	1	1	100.00
V2	stress	rv_timer_stress_all	3.440s	3.106ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.680s	11.549us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.560s	21.576us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.910s	122.085us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.910s	122.085us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.750s	50.399us	1	1	100.00
		rv_timer_csr_rw	0.800s	13.012us	1	1	100.00
		rv_timer_csr_aliasing	0.890s	20.213us	1	1	100.00
		rv_timer_same_csr_outstanding	0.910s	15.749us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.750s	50.399us	1	1	100.00
		rv_timer_csr_rw	0.800s	13.012us	1	1	100.00
		rv_timer_csr_aliasing	0.890s	20.213us	1	1	100.00
		rv_timer_same_csr_outstanding	0.910s	15.749us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	rv_timer_sec_cm	1.240s	344.249us	1	1	100.00
		rv_timer_tl_intg_err	1.450s	129.594us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.450s	129.594us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	0.780s	196.695us	0	1	0.00
V3	max_value	rv_timer_max	0.600s	45.531us	0	1	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	38.750s	6.072ms	1	1	100.00
V3		TOTAL			1	3	33.33
		TOTAL			16	19	84.21

Failure Buckets

• UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 2 failures:

  • Test rv_timer_min has 1 failures.

    • 0.rv_timer_min.26453387380882768722020699086776695752528296795258175638230464860113367361902
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log

        UVM_FATAL @ 196694593 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x39a92704) == 0x1
        UVM_INFO @ 196694593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_timer_random_reset has 1 failures.

    • 0.rv_timer_random_reset.17572114685788505802715215069488766344212931914758922277895654246578436485570
      Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log

        UVM_FATAL @ 676697069 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xf8f97f04) == 0x1
        UVM_INFO @ 676697069 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:

  • Test rv_timer_max has 1 failures.

    • 0.rv_timer_max.102113911760734418614096567302047466374279192783048038327021709359197826760081
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log

        UVM_ERROR @  45530675 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
        UVM_INFO @  45530675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---