SPI_DEVICE/1R1W Simulation Results

Wednesday October 22 2025 16:03:16 UTC

GitHub Revision: fc2d73b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	5.118m	61.233ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.250s	218.688us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	1.150s	45.889us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	27.590s	2.701ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	6.670s	942.636us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.100s	130.862us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.150s	45.889us	1	1	100.00
		spi_device_csr_aliasing	6.670s	942.636us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	0.810s	25.983us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.490s	81.688us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.090s	17.314us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.020s	1.168us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	0.650s	3.021us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	0.760s	20.317us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	0.760s	20.317us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	2.570s	8.053ms	1	1	100.00
		spi_device_tpm_sts_read	0.800s	63.612us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	0.740s	17.436us	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	6.660s	4.357ms	1	1	100.00
		spi_device_flash_all	23.490s	4.678ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	1.980s	29.286us	1	1	100.00
		spi_device_flash_all	23.490s	4.678ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	1.980s	29.286us	1	1	100.00
		spi_device_flash_all	23.490s	4.678ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	23.490s	4.678ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	7.480s	1.103ms	1	1	100.00
		spi_device_flash_all	23.490s	4.678ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	7.480s	1.103ms	1	1	100.00
		spi_device_flash_all	23.490s	4.678ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	7.480s	1.103ms	1	1	100.00
		spi_device_flash_all	23.490s	4.678ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	7.480s	1.103ms	1	1	100.00
		spi_device_flash_all	23.490s	4.678ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	7.480s	1.103ms	1	1	100.00
		spi_device_flash_all	23.490s	4.678ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	8.350s	2.686ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	2.030s	119.241us	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.030s	119.241us	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.030s	119.241us	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	12.270s	1.096ms	1	1	100.00
		spi_device_read_buffer_direct	10.460s	1.376ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.030s	119.241us	1	1	100.00
		spi_device_flash_all	23.490s	4.678ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	23.490s	4.678ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	23.490s	4.678ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.520s	488.915us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.520s	488.915us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	5.118m	61.233ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	4.206m	56.259ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.010s	52.156us	1	1	100.00
V2	alert_test	spi_device_alert_test	0.830s	204.238us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.020s	30.695us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.440s	925.118us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.440s	925.118us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.250s	218.688us	1	1	100.00
		spi_device_csr_rw	1.150s	45.889us	1	1	100.00
		spi_device_csr_aliasing	6.670s	942.636us	1	1	100.00
		spi_device_same_csr_outstanding	3.810s	603.952us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.250s	218.688us	1	1	100.00
		spi_device_csr_rw	1.150s	45.889us	1	1	100.00
		spi_device_csr_aliasing	6.670s	942.636us	1	1	100.00
		spi_device_same_csr_outstanding	3.810s	603.952us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	0.990s	56.757us	1	1	100.00
		spi_device_tl_intg_err	6.300s	366.206us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	6.300s	366.206us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	22.350s	14.267ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.96085406111961970476388899034724891105840570488506402514764900298592221445838
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @    978227 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[42])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    978227 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @    978227 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[938])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.1872476726591108610733430139519355505723339879888405462642797261019669597401
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @    994974 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x862304 [100001100010001100000100] vs 0x0 [0])
        UVM_ERROR @   1043974 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x953b36 [100101010011101100110110] vs 0x0 [0])
        UVM_ERROR @   1124974 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7c0c35 [11111000000110000110101] vs 0x0 [0])
        UVM_ERROR @   1127974 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x29955c [1010011001010101011100] vs 0x0 [0])
        UVM_ERROR @   1214974 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc7df58 [110001111101111101011000] vs 0x0 [0])