SPI_HOST Simulation Results

Wednesday October 22 2025 16:03:16 UTC

GitHub Revision: fc2d73b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	57.000s	4.412ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	1.000s	103.594us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	1.000s	39.645us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	2.000s	223.780us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	2.000s	78.199us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	30.524us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	1.000s	39.645us	1	1	100.00
		spi_host_csr_aliasing	2.000s	78.199us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	1.000s	30.925us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	1.000s	117.106us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	8.000s	64.099us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	6.000s	56.743us	1	1	100.00
		spi_host_error_cmd	6.000s	47.157us	1	1	100.00
		spi_host_event	37.000s	2.459ms	1	1	100.00
V2	clock_rate	spi_host_speed	12.000s	828.606us	1	1	100.00
V2	speed	spi_host_speed	12.000s	828.606us	1	1	100.00
V2	chip_select_timing	spi_host_speed	12.000s	828.606us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	10.000s	61.898us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	5.000s	25.267us	1	1	100.00
V2	cpol_cpha	spi_host_speed	12.000s	828.606us	1	1	100.00
V2	full_cycle	spi_host_speed	12.000s	828.606us	1	1	100.00
V2	duplex	spi_host_smoke	57.000s	4.412ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	57.000s	4.412ms	1	1	100.00
V2	stress_all	spi_host_stress_all	15.000s	1.500ms	1	1	100.00
V2	spien	spi_host_spien	48.000s	17.852ms	1	1	100.00
V2	stall	spi_host_status_stall	1.650m	3.216ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	3.000s	325.413us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	6.000s	56.743us	1	1	100.00
V2	alert_test	spi_host_alert_test	2.000s	18.743us	1	1	100.00
V2	intr_test	spi_host_intr_test	1.000s	27.403us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	1.000s	586.384us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	1.000s	586.384us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	1.000s	103.594us	1	1	100.00
		spi_host_csr_rw	1.000s	39.645us	1	1	100.00
		spi_host_csr_aliasing	2.000s	78.199us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	27.008us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	1.000s	103.594us	1	1	100.00
		spi_host_csr_rw	1.000s	39.645us	1	1	100.00
		spi_host_csr_aliasing	2.000s	78.199us	1	1	100.00
		spi_host_same_csr_outstanding	1.000s	27.008us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	1.000s	143.781us	1	1	100.00
		spi_host_sec_cm	2.000s	76.573us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	1.000s	143.781us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	52.000s	4.043ms	1	1	100.00
		TOTAL			26	26	100.00